UCIe Face-Up IP Taped Out by GUC on TSMC N5 for SoIC-X, Targets AI and HPC Applications

Global Unichip Corp. (GUC) has taped out a Universal Chiplet Interconnect Express (UCIe) PHY Face-Up IP on TSMC’s N5 process, designed for integration with TSMC’s SoIC-X technology. The IP, aimed at AI, HPC, xPU, and networking applications, operates at 36Gbps per lane with a bandwidth density of 1.5TB/s per mm of die edge. It incorporates Adaptive Voltage Scaling (AVS), achieving up to 2x better power efficiency by optimizing supply voltage and drive strength via a training algorithm that ensures reliable operation under varying conditions. The IP also features proteanTecs’ I/O signal quality monitors for real-time performance tracking without interrupting data transfer.

The chip was assembled using TSMC’s SoIC-X and CoWoS packaging technologies. GUC previously demonstrated UCIe-32G silicon on TSMC’s N3P process at the TSMC 2025 North America Technology Symposium and taped out a UCIe Low Power (LP) solution on N5 in 2024. The Face-Up UCIe LP IP supports SoIC-X bottom die configurations, enabling robust die-to-die interconnects. GUC is developing UCIe 64G IP, with a planned tape-out by the end of 2025 to address increasing bandwidth demands in chiplet-based systems.

For integration, GUC provides bridges for AXI, CXS, and CHI buses using the UCIe Streaming Protocol, optimized for high traffic density, low latency, and low power. The...