InPsytech Advances Chiplet Integration with UCIE 2.0-Compliant F2F SoIC Tape-Out for AI and HPC

InPsytech has taped out a design for TSMC’s Face-to-Face (F2F) System-on-Integrated-Chip (SoIC) technology, compliant with the UCIE 2.0 standard. The design utilizes Through-Silicon Via (TSV) technology for signal transmission and power delivery, enhancing flexibility and efficiency in 3D heterogeneous chiplet integration. InPsytech also introduced wafer-level and package-level verification solutions for TSMC’s SoIC processes to streamline IC design validation.

As an IP partner in Intel’s Foundry Accelerator IP Alliance and Samsung’s SAFE program, InPsytech integrates its solutions into these foundry ecosystems, supporting applications in high-performance computing servers and edge AI devices with improved latency and bandwidth. Howard Ro, General Manager of InPsytech, noted the tape-out reflects collaboration with industry partners and customer confidence in their capabilities. InPsytech plans to deepen domestic and international partnerships to advance global semiconductor technology.