Architecture-stage EDA Tool VisualSim to Design UCIe-based Multi-die SoC

While performance is the key factor for commercial success of any semiconductor chip, the development cost and time plays an even more critical role in the successful launch of the chip. Extremely complex and expensive semiconductor fabrication technologies such as nano-sheet FETs are used today at 3 nm and 2 nm technology nodes. Due to which the development cost of complex monolithic SoC made at these nodes is spiraling to unacceptable levels, suggesting complete SoC on a monolithic silicon die is no longer economically-feasible. It is becoming extremely challenging to achieve acceptable production yield rate by the most advanced semiconductor chip foundries for large die size monolithic chips. IP functional blocks such as analog, power management and interface reap no benefits at deep nodes; alternatively making them at mature nodes such as 28nm is more beneficial. With economy of scale not working for monolithic ICs, Chip industry is rapidly migrating to multi-die heterogeneous integration of dies from different vendors made at different nodes packaged in a single 3D and 2.5D chips. This trend throws big challenge of advanced packaging as well as increase in complexity of design. Stakeholders in this industry have come together to find common standards for this fast-emerging market. Universal Chiplet Interconnect Express (UCIe) is the new die-to-die (D2D) interconnect open...