Muse Semiconductor and True Circuits Launch Low-Cost PLL IP Program for Universities

Muse Semiconductor and True Circuits have launched a University IP Access Program that gives students and researchers access to True Circuits' phase-locked loop (PLL) hard macros, a type of pre-verified circuit design, at low cost through Muse's multi-project wafer (MPW) service, which lets multiple designs from different customers share space on a single chip-manufacturing run to reduce cost. A PLL is a circuit used to generate precisely timed clock signals that keep different parts of a chip synchronized, and it's a component many student chip designs need but that can be costly and time-consuming to build from scratch.

 

The goal of the program is to let students and faculty use commercial-grade, already-proven IP rather than spending time and limited budget developing their own PLLs, freeing them up to focus more of their research on developing new semiconductor technologies. Both companies frame the program as an extension of work they've already been doing with universities to support semiconductor research, aimed specifically at making it easier and more affordable for academic teams to access commercial-quality IP while also giving students exposure to how IP licensing works in a real commercial setting.

 

Bill Isaacson, general manager of Muse Semiconductor, said the program gives universities an easy way to ac...