Tensordyne Tapes Out Napier AI Inference Processor on TSMC 3nm, Reports 17x Tokens Per Watt vs NVIDIA Blackwell

Tensordyne, a new entrant into AI Inference chip world,  has announced the tape-out of its Tensordyne Napier (TDN) AI inference system. The system is designed to address the trade-off between inference speed and cost efficiency.

The platform was developed in partnership with Broadcom and HPE Juniper Networks. It combines logarithmic AI math, tightly integrated memory architecture, and high-performance scale-up interconnect. The Napier processor has completed tape-out and is now in production at TSMC on the 3nm process node.

Tensordyne has a pipeline of hyperscaler, neocloud, and sovereign AI infrastructure operators evaluating the platform. This includes more than a dozen Letters of Intent tied to system demos and early access engagement. Engagements are advancing toward benchmarking, beta deployment, and broader infrastructure planning that represents more than $200 million in forecasted Napier system demand. The announcement precedes an anticipated Series D financing later this year.

Tensordyne redesigned core components of the AI inference stack across math, compute, memory, and networking. TDN Math replaces large-scale multiplication operations with addition-based computation using logarithmic mathematics. TDN AIP integrates substantial fast SRAM alongside HBM memory in each processor. TDN Link provides any-to-any scale-up interconnect with sub-...