3-D semiconductor innovation by IRT Nanoelec, CEA-Leti, STMicro and Mentor

In a three-dimensional semiconductor device fabrication achievement, IRT Nanoelec, CEA-Leti, STMicroelectronics and Mentor Graphics have developed a 3DNoC IC device based on a 2D semiconductor die that can be used in a stand-alone applicative mode, and also in a 3D stack with several dice, to multiply the processing performance of the system. "The technology developed for this realization can be easily used and transferred to address mixed-technology applications, such as imagers and RF transceivers, or complex digital processing, such as high-performance computing and programmable devices," said Severine Cheramy, IRT 3D program director. "In parallel with these results, we are working on developments that address more fine-pitch 3D technology than those used in the 3DNoC demonstrator and solutions for thermal dissipation, temporary bonding and stress issues." 3D-stacking enables integration of different technologies and simplifies the use of small-sized dice to improve modularity and increase yield which reuses the die instead of IP in case of a monolithic integrated circuit type SOC. Such IP physical blocks are called chiplets. 3DNoC chip was defined and designed by Leti, with the direct support of STMicroelectronics, using a specific add-on 3D design kit and a set of 3D sign-off verification tools provided by Mentor Graphics. CMOS technology, 3D technology and pa...