HiSilicon uses Synopsys IC Compiler to tape-out 50+ million instance SoC

Synopsys said HiSilicon has taped out a 50+ million instance ARM Cortex-A15 processor based system-on-chip (SoC) using Synopsys' IC Compiler which offers improved clock tree synthesis (CTS) and faster top-level closure for designing gigascale SoC. "At HiSilicon, we continually innovate to deliver complex SoC solutions that are well differentiated in terms of performance and functionality," said Teresa He, President, HiSilicon Technologies Co., Ltd. "We have long recognized the importance of working with leading-edge partners like Synopsys to enable us to achieve our design objectives. On this multi-million instance SoC tapeout, we used the latest technologies in the Galaxy Implementation Platform to develop a correlated and predictable design closure flow that met our aggressive performance targets for on-time delivery." The 50+ million instance HiSilicon SoC targeting the wireless chipset market contains multiple ARM Cortex-A15 processors, peripheral logic and memories. It was implemented hierarchically and fabricated on a TSMC 28HPM process using TSMC standard cell libraries and fast cache instance memories. The high operating frequency meant that clock skew and on-chip-variation (OCV) tolerance targets were very low. At the same time, due to the tight schedule, a correlated and convergent flow for faster design closure was a key implementation requirement. HiSilicon ...