Less-than-40nm node chips consuming 1/4th of silicon wafers, as per IC Insights

IC Insights has come out with its latest report on consumption of silicon wafers for different technology nodes. IC Insights finds more than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries (or feature sizes) smaller than 40nm. Below is the details of latest analysis released by IC Insights: Installed capacity is divided into six categories based on the minimum geometry of the processes used in wafer fabrication. The six categories range from <40nm; ≥40 - <60nm; ≥60nm - <80nm; ≥80nm - <0.2µ; ≥0.2µ - <0.4µ; ≥0.4µ. At the end of 2012, about 27% of global wafer capacity was for devices having geometries smaller than 40nm (Figure 1). Such devices include high-density DRAM, which are typically built using 30nm- to 20nm-class process technologies; high-density flash memory devices that are based on 20nm- to 10nm-class processes; and high-performance microprocessors and advanced ASIC/ASSP/FPGA devices based on 32/28nm or 22nm technologies. About 22% of global capacity is dedicated to the ≥80nm - <0.2µ segment, which includes the 90nm, 0.13µ, and 0.18µ process generations. This “mature” process is widely used by pure-play foundries including TSMC, UMC, GlobalFoundries, SMIC, and TowerJazz and to manufacture a broad range of products for their diverse customer bases. The least common technologies, at least in ...