Ericsson uses in-house developed complex ASIC for its 4th gen IP n/w system

At the MPLS & Ethernet World Congress in Paris, Ericsson has announced in-house ASIC, the Ericsson SNP 4000 network processing chipset, and extension of the Ericsson IP Operating System as the common platform across the entire IP portfolio. Ericsson SNP 4000 features packet processing capacity with an ASIC integrated with thousands of processor cores supporting next-gen speed of 1Tbps and supporting applications with millions of subscribers. By using hyper-threaded architecture running on the Linux OS with full support for GNU based C/C++ tool chain, the SNP 4000 is designed for speed and power efficiency. Michael Howard, principal analyst of carrier networks at Infonetics Research, says: "The announcements Ericsson made today are noteworthy. With rapid growth in smart devices and personalized services, one of the biggest challenges presently facing operators is to keep up with bandwidth demand while simultaneously delivering complex services. While service provider SDNs will greatly simplify functions like dynamic service chaining, these SDN capabilities will still rely on packet processing. I'm sure service providers will be interested in the service capabilities that the SNP 4000 enables, since it is based on a new hyper-threaded architecture, running thousands of "run-to-completion hardware threads" or "cores." It is an industry first to support this many cores. Th...