EE Students: Get you chip prototype done at ST fab through CMP

STMicroelectronics and CMP have announced that ST’s H9A CMOS process (at 130nm lithography node), is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. The diffusion of the silicon wafers will take place at the ST plant in Rousset, near Aix-en-Provence (France). ST is releasing this process technology to third parties as a foundry service for a well-established analog platform and for new developments in the More than Moore applications such as energy harvesting, autonomous intelligence, and home-automation integrated systems. The introduction in CMP’s catalogue of ST’s H9A (and its derivative H9A_EH) process builds on the successful collaboration that has allowed universities and design firms to access leading-edge and previous CMOS generations including 28nm CMOS, 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003) through the ST Site of Crolles. CMP’s clients also have access to 28nm FD-SOI, 65nm SOI and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics. More than 200 universities and companies have received the design rules and design kits for the ST 65nm bulk and SOI CMOS processes. Since CMP started offering the ST 28nm CMOS bulk technology in 2011, some 100+ universities and microele...