VLSI chip design 2013: Latest trends from concept to product

Date: 04/03/2013
When it comes semiconductor chip design, there is one task, which is nearly a pure software; that is verification. India is attractive destination for finding resources on VLSI chip design verification talent. Around 70% of Indian VLSI design Services Companies are engaged in verification services. Verification engineers are not really so much concerned or exposed to physical design of the chip such as whether it is 14nm, double pattering, FinFET, EUV and any such physical design challenges of chip fabrication. Verification engineers focus on verifying digital and analog and mixed signal function including complex graphic processor to simple logic gate functionality. It all about programming and testing the code in the most popular language called VHDL.

Another software-type expertise evolved in recent years is virtual prototyping. Virtual prototype gives the system design engineers virtual silicon equivalent before the chip gets taped out from the fab. So that the embedded systems developer can start checking the code with virtual prototype at the early stage of product design and so that the overall product development time can be reduced.

This writer recently interacted with three senior executives of World’s number one EDA software vendor Synopsys to get views on latest trends in chip design.

A. Interaction with Mr. Manoj Gandhi, Senior Vice President and General Manager, Verification Group, Synopsys on Verification trends:

Skills required for verification engineer with the advancement of nodes/technologies:

Manoj: I think India or the engineers from India or students from Indian engineering schools, have outstanding opportunity in verification, mainly because as the complexity has grown over the years, verification has become more like a software. So long time back people used to do directed test or they used to do more like a brute-force way of verification using sometimes gate-layout simulation, but if you see the last five or six years, in fact Synopsys brought high level language Verilog to the industry. So that’s very object oriented. And to be able to do verification, you need to learn all object oriented skills and also the complexity in hardware designing is much more.

India is very strong in the software side so that it creates a good opportunity for the engineers from these schools here(India) to become a good verification engineers. So the basic foundation is a good software skill. Now, that’s not sufficient because most of the applications people want to design for low power. Low power VLSI design verification has evolved just in last two to three years. And in fact Synopsys acquired this company ArchPro, they are the leaders in that space and then we are very strong investment in that space. It brought new techniques in verification as well as it brought new language like UPF and so all the engineers have to learn all of that as well.

Importance of verification engineers for semiconductor chip companies:

Manoj: I think verification engineers are going to be more and more critical for many companies. They are telling us that verification will determine design. How good is your verification team, as well as -- do you have time to do full verification, if not, they have to cut some of the features. So verification has become a bottleneck.
There is a trend where they want to make design engineers more verification aware, as well as you know -- I am sure that some of the verification engineers are good at design as well. There are many companies, which are now giving more importance to verification engineering management. So my prediction is that overtime, verification engineers are going to be equally critical.

On the growing trend of IP reuse:

Manoj: There is a lot more IP re-use because when you are designing very complexes SOCs and there is time to market pressure, if you miss out a particular product window, you miss out a big customer. All that creates a lot of pressure to have the SOCs done on time and to do that it is much more cost effective to acquire IPs from, less process, or also within that large companies they are reusing lot of IP so that creates a new challenge.

To quality check third party IPs:

Manoj: We sell a verification IP for that. So, this automates making sure that your IP is a high quality. So, that is a new business we are investing, where we have very strong market presence. I see that as one of the critical areas to solve this issue of how to make sure that the IP reused is manageable, how to automate more and more verification around it.

Trends in catching bug in early stage of verification:

Manoj: People used to do low power (verification) at gate level. Now we are doing that at RTL using the technology, which ArchPro (acquired by Synopsys) created, which Synopsys has now. We started to define how to do that type of, how do we find those bugs early in the design process, so we are doing RTL now. Similarly we recently acquired two important companies, EVE and SpringSoft. SpringSoft is the leader in the deeper verification, and EVE is upcoming new emulation company which is doing very well. They have very strong customers and we are going to invest tremendously in both of these companies.

So basically, think of verification is like this that we have very high level language, like system VHDL and then you sort of define all your functionality in that language. Our software automates the process of creating tests as well as running thousands of machine run verification for a design.

B. Interaction with Mr. Joachim Kunkel, Senior Vice President and General Manager, Solutions Group on Virtual prototyping trends

Key Trend and applications of virtual prototyping:

Joachim Kunkel: What we are seeing is virtual prototyping has established itself as methodology for early software development in two industries, in the mobile/portable consumer (electronics) industry and the automotive industry. What we are seeing in automotive industry is customers are using our virtualizer tools for describing the ECU for a virtual prototype of ECU and combining that with simulation prototype model for mechanical portion.

Relying on Virtual Prototype for complete development of product:
Joachim Kunkel: For what we are seeing is that our customers are doing pretty much the complete development of virtual prototype and then obviously they take the software that they have developed and put it on a real test bench that includes the actual electronics.

On evolving standards for Virtual Prototyping:

Joachim Kunkel: Well if you are looking at standard for virtual prototyping there is basically one element there that needs to be standardized, there may be two! which is mostly how do you ensure that models of processors and models of peripherals, etc, those are readable for number of different tools and you are not going to mimic models with single propriety type of tools. That holding to a complex tool of System C standard. There are models of peripherals and models of processors that are system C complaint, typically at transaction level.

Leveraging cloud computing in offering VLSI services on net to SMEs:

Joachim Kunkel: In fact we have, as a company we created cloud computing capabilities and made our tools available on the cloud many years ago. The issue that we have been facing is that many customers so far had not been willing to put their engineering data into the cloud. Technically it is not an issue, what we are dealing with is more on the IP protection.

C. Interaction with Mr. John Chilton, Senior Vice President Marketing, Synopsys:

On the trend of first time successful tape-out:

John Chilton: There was a time 10 years ago, people really expected chips to not work and spin (re-design) them, People really don’t expect them anymore now. So if you are doing chip design and trying to get chips to market very quickly, you don’t have time to spin them. Not only geometries but also time to the fab getting longer. You know, you are talking about 4-5 months to get from the fab, if you spin the chip, forget it! Synopsys is leveraging its advanced tools to address this challenge of no re-spin.

Collaboration between EDA software, fab and IC-design companies:

John Chilton: Verification has become much-much more exact now. OVM is a powerful methodology. The chance of killer bug is less now. We are working on the libraries and IPs for 14nm with the foundries using our tools. So that means by then once the customer get involved, we are already bent down that road with the foundry, we have already solved many of the issues and often reach the foundry and design(fabless semiconductor companies) who are working together on the design.

Examples of technology improvement to save time and prevent bugs:

John Chilton: You have to get the spice models right. You develop the transistor with TCAD, that simulates the basis transistor at atomic level. The fabs can’t experiment any more -- its too expensive, so they have to simulate, so they are simulating with TCAD and then verifying in silicon what they are going to see, TCAD tools also help to do spice test, you need spice model, so that you need to able to run spice and see what the basic parameters are, see what’s the basic speed of the transistors going to be.
So, now you have an early problem with the lithography, you have to get the lithography right, at 20nm you got to go for double patterning. Double pattering means you need two masks, and you got to do coloring. We are the only company to tape out production chips in 14nm node.

Business impact of node jump:

John Chilton: The main reason people move from 40 to 28nm is not speed or power but its cost, if you are my competitor you move to 28nm, and you are the making chips for half what I am, you are going to kill me (in terms of business), so I have to move.
John Chilton finds the cost advantage of deeper nodes still going to continue for some more time.

EDA Market nuggets from John Chilton:
Synopsys is 2nd biggest vendor of Silicon IPs with revenues around US$300 Million and is growing around 20%. He says “IP business is not easy, you got to be perfect”.

Synopsys share in India EDA market:
He says “There is local Indian market and then the multinational companies, Overall India is our 2nd largest market after U.S.”