Marvell achieve breakthrough in co-packaged optics architecture

Marvell announced the advancement of its custom XPU architecture with co-packaged optics (CPO) technology. Building on its recently announced custom high-bandwidth memory (HBM) compute architecture, Marvell is now extending its custom silicon leadership by enabling customers to seamlessly integrate CPO into their next-generation custom XPUs and scale-up the size of their AI servers from tens of XPUs within a rack currently using copper interconnects to hundreds across multiple racks using CPO, enhancing AI server performance. The innovative architecture enables cloud hyperscalers to develop custom XPUs that achieve higher bandwidth density and deliver longer reach XPU-to-XPU connections within a single AI server – with optimal latency and power efficiency. The architecture is now available for Marvell customers' next-generation custom XPU designs. The Marvell custom AI accelerator architecture combines XPU compute silicon, HBM and other chiplets with Marvell 3D SiPho Engines on the same substrate using high-speed SerDes, die-to-die interfaces and advanced packaging technologies. This approach eliminates the need for electrical signals to leave the XPU package into copper cables or across a printed circuit board. With integrated optics, connections between XPUs can achieve faster data transfer rates and distances that are 100X longer than electrical cabling. This enables scal...