Agile Analog launches complete analog IP subsystem for RISC-V applications

Agile Analog has announced launch of its first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona (5-9 June). The initial subsystem includes all the analog IP required for a typical battery-powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters. This unique, process-agnostic, customisable and digitally wrapped analog IP subsystem will help solve many of the issues that System on Chip (SoC) designers currently encounter, as it pairs with a RISC-V core to form a complete solution. Chris Morrison, Director of Product Marketing at Agile Analog, explains: “The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs.” Chris adds: “With our RISC-V analog IP subsystem, it’s possible to access the appropriate analog IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications. As with all of the Agile Analog IP, this subsystem is customisable to give the exact feature set required for the ap...