VLSI SoC layout design: FlexNoC phy interconnect IP reduce P&R iterations

Arteris is offering the new FlexNoC Physical interconnect IP for VLSI physical design of SoC chips. The layout friendly FlexNoC Physical IP is designed to reduce the timing issues experienced in the layout stage, reducing place and route (P&R) iterations and engineering change orders (ECOs). Designed for using lesser wires, FlexNoC Physical interconnect IP offers fine-grained pipeline register placement nearly anywhere in the interconnect, and allows distributed IP placement. FlexNoC Physical interconnect IP improves layout quality-of-results (QoR) and productivity by importing user-defined and production floorplans, automatically configuring pipelines to meet timing closure constraints, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC, explains Arteris. The benefits of FlexNoC Physical IP as per Arteris includes: Reduces or eliminates excessive P&R iterations – To resolve timing closure errors on long paths, SoC designers often have to iterate over multiple P&R runs, which can be very expensive. Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of timing closure issues during layout. Eliminates trial-and-error timing closure with automated pipeline configuration – By analyzing the actual interconnect IP in the front-end design phase and automa...