Aldec adds plotting feature in its new version of verification platform

Aldec, Inc. has released its enhanced version of its VLSI chip design verification platform called Riviera-PRO 2013.02. The enhancements include visual debugging tools that improve the presentation of simulation results. Riviera-PRO 2013.02 includes a Plot window supporting four different plot types to visualize large data sets, and also to analyze relations between any objects within a design with no additional programming required. Aldec explains: The traditional approach to analyzing objects in an HDL design, based on digital waveforms, dataflows, memory, and hierarchical viewers, may not be optimal for all applications. For example, in a waveform signal values are represented with respect to time, allowing many parameters to be verified in a digital system. However, when large data sets are used or the correlation between non-linear values must be analyzed, engineers will often have too many screens of illegible alphanumeric data to review, losing precious time analyzing or investigating alternative methods to represent this data. For this reason, traditional tools might not be the most efficient debugging solution for data-intensive applications such as image processing, digital filtering, industrial control systems, telecommunication systems and certain embedded systems. “A picture is worth a thousand words”, said Dmitry Melnik, Product Manager, Aldec Software Di...