By using Vision HDL Toolbox from MathWorks, VLSI design engineers can generate vendor independent HDL code to run pixel-streaming algorithms on FPGA and ASIC chips from leading vendors.
The design framework inside the toolbox supports multiple interface types, frame sizes, and frame rates, including high-definition (1080p) video. HDL implementations supporting architecture process the data by having a library of image processing and computer vision algorithms specifically designed for FPGA and ASIC implementation.
The tool box supports automatic conversion between frames of various sizes and pixels and with HDL Verifier, designers can connect the algorithms running on the FPGA or ASIC with frame-based test models running in MATLAB or Simulink.
"FPGAs in particular are an increasingly popular platform for image processing and computer vision systems," said John Zhao, marketing manager at MathWorks. "The new Vision HDL Toolbox has been created to help developers prototype and implement systems faster, with shortened design cycles, and more efficiently, through the ability to identify design errors early in the workflow and minimize the time needed for writing HDL code."
Some of the image processing features in this tool includes: image enhancement, filtering, morphology, and statistics, Frame-to-pixel and pixel-to-frame conversions, Video synchronization signals for handling nonideal timing and resolution variations, Configurable frame rates and frame sizes, including 60FPS for high-definition (1080p) video, and Support for HDL code generation and real-time verification.