The semiconductor manufacturing ecosystem, mainly the semiconductor equipment companies are increasingly collaborating to develop solutions for volume manufacturing of chips in the nodes of less than 14 nm and also on wafer sizes of 450mm.
Semiconductor equipment manufacturer ASML and imec are extending partnership by launching Advanced Patterning Center, which going to work on lithography technology in the nodes of less then 14nm.
imec and ASML to combine their technologies to print nanometer size patterns more precisely and uniformly on the semiconductor wafer. The Advanced Patterning Center to use actual devices to analyse and optimize process steps as well as materials and device architecture choices, while applying integrated metrology.
Imec's clean room infrastructure (full 300mm pilot line with extension to 450mm) and ASML's most advanced scanners, metrology systems and lithography equipment are used in the Advanced Patterning Center. The combined research effort is aimed at providing enhanced lithography equipment for deeper nodes as well 450mm wafer processing.
At the nodes of 14 nm and lower, it needs extraordinary microscopes to see the changes after etching and other processes. Bruker, an expert in this area has joined SEMATECH to collaborate with metrology experts at SEMATECH to develop high-resolution atomic force microscope (AFM) based defect analysis capabilities, linked to material data provided by transmission electron microscopy (TEM) analysis with advanced energy dispersive X-ray spectroscopy (EDX) and electron energy loss spectroscopy (EELS). These techniques will provide the high-resolution imaging and compositional data on the scale of a few nanometers, which is invaluable for in-line defect analysis.
SUSS MicroTec’s photomask equipment division has partnered with SEMATECH to investigate and develop extreme ultraviolet lithography (EUVL) substrate and blank cleaning technologies that will accelerate process availability for extreme ultraviolet pilot line manufacturing.
SUSS MicroTec’s photomask equipment division is said to collaborate with the consortium’s EUV mask experts to focus on improving the cleaning yield on EUVL mask blanks, patterned masks and non-patterned EUVL substrates. The long-term goal of this collaboration is to increase the manufacturing yield for substrates and mask blanks with the lowest defect counts at nonprintable defect sizes, according to the release by SEMATECH.
To update you on one more recent big news, Applied Materials and Tokyo Electron merged to speedup the innovation in deep node manufacturing
The result of all these going to be fast development of sub-10nm, 450 mm fab, which can make billions of chips.