Mentor Graphics has added intelligent software-driven verification (iSDV) to the Questa functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. iSDV features helps VLSI designers to find more system level design bugs earlier in the verification process during simulation or emulation.
“To fully verify our high performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa’s intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule,” said Galen Blake, Altera senior verification architect. “With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence.”
“Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose,” said Mark Olen, verification solutions technologist, Mentor. “Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level.”
Questa iSDV automates writing directed tests in C to verify multi-core, multi-threaded designs.
The Questa iSDV tool is available immediately as part of the Questa functional verification platform.