Jasper Design Automation to demonstrate its latest Apps verification solutions in booth #2346 at the Design Automation Conference (DAC), June 2-6, 2013 in Austin, Texas.
Customer seminars at DAC include presentations on:
Sequential Equivalence Verification
When: Monday, June 3 at 10:00 a.m.
Wednesday, June 5 at 1:30 p.m.
Integrated Flow with ARM
Who: Duolog Technologies and Jasper Design Automation
When: Monday, June 3 at 11:00 a.m. and 3:00 p.m.
Tuesday, June 4 at 10:00 a.m. and 2:30 p.m.
Wednesday, June 5 at 10:00 a.m. and 3:00 p.m.
Security Path Verification
Who: Gila Logic
When: Monday, June 3 at 11:30 a.m.
Wednesday, June 5 at 11:30 a.m.
Adopting Formal to Increase Productivity and Quality in Verification and ARM-Based CPU Subsystem
When: Monday, June 3 at 1:30 p.m.
Tuesday, June 4 at 4:00 p.m.
Formal – An integral Part of Chip Design
When: Tuesday, June 4 at 10:00 a.m.