At 14 or 16 nm node and at further deeper nodes there is a huge challenge to interconnect complex subsystems on the chip. Take the example of Xilinx 3D FPGA, it packs 19 billion transistors on a chip manufactured using 20nm node, you need a extremely smart interconnect to connect multiple processors and other accelerators in these devices. The multi-storey metal layers on these highly integrated chips have grown too tall to manage them, making a fabrication with plain old interconnect technology near impossible. Through a microscope they look similar to a tall building structure. Serial bus is essential and acts like a network inside the chip. The interconnect network inside the chip works much like the wired ethernet like computer-network. When you have a multicore processors of heterogenous type on a single chip making them access cache memory with coherency is big challenge. It is required for processors with the different instruction set architecture to coherently share data in cache memory.
If you ask what are the applications for such heterogenous processor core SOC chips, they include advanced driver assistance systems in autonomous cars, and many such machine vision demanding applications. NXP Semiconductors is using Ncore interconnect IP in its microcontrollers for automotive applications. Some of the other applications suggested includes high-definition television, enterprise storage, micro-server and networking.
If interconnect is causing the bottleneck in efficiently utilising the real estate space on a chip and also to utilise a maximum performance of each processor element, the new flexible and configurable interconnect IP such as Ncore interconnect IP launched by Arteris clears such bottlenecks so that the processor can work at higher frequency. Ncore interconnect IP also said to simplify timing closure because it is more friendly to industry-standard synthesis-place-and-route tools.
Arteris Ncore interconnect IP is Praised for its excellent configurability and flexibility, which is difficult in case of other presently available cache coherent interconnect which are centralised and uses something called crossbars. Due to this flexibility and configurablity of Ncore, SOC design engineers can select the number of coherent agents and memory interface ports , numbers and sizes of configurable snoop filters, and numbers and sizes of proxy caches and last-level caches. The three Key units of Arteris Ncore interconnect IP are coherent agent ports, memory interfaces, and snoop filters which can be precisely controlled and configured, helping optimising physical design of SOC by easing back-end placement and timing closure due to distributed hardware architecture.
Below is the further explanation by Arteris on coherent agents distributed architecture, snoop filters, and Proxy Caches:
Heterogeneous Coherent Agents - Allows smooth interoperability of different coherent protocol implementations, cache state models and cache organizations, enabling use of coherent IP from multiple vendors and internal development teams.
Distributed Architecture – Eases floor planning and timing closure while enabling flexible clock and power management.
Multiple Configurable Snoop Filters – Configure the organization, size and associativity of multiple individual snoop filters based on caching agent characteristics in the system, reducing the overall memory footprint required for the system.
Proxy Caches – Enable non-coherent IP to achieve the benefits of system-wide coherency.
These components can be replicated with a configurable number of ports per component, allowing the interconnect IP to scale to different processor requirements.
VLSI EDA software design vendor Synopsys is a first company to announce verification solution for Ncore interconnect IP.
The Synopsys verification solution delivers UVM testbench logic that integrates with Arteris Ncore interconnect testbenches allowing connectivity of new subsystem level tests, monitors, coverage and performance tests, and analysis for faster verification. The verification solutions from Synopsys validate the coherency of the system and correctness of data flow across the network on chip. Synopsys' Verdi Performance Analyzer which is part of the solution provides debug capabilities for performance issues across the SoC. In addition, Synopsys' Platform Architect MCO helps in analysing Arteris Ncore interconnect subsystem models, allowing designers to optimize architecture performance and power earlier.
Arteris has used ARM Cycle Models for use in hardware and performance verification Ncore Cache Coherent Interconnect IP.
All this points to a trend of designing your own custom SoC, provided if there is business value in that. Latest news on this trend is Google designing its own chips for machine learning.