Compression IP for MIPI DSI IP enables high resolution at lower bandwidth

Synopsys DesignWare MIPI DSI IP and Hardent VESA Display Stream Compression IP are made compliant and interoperable to reduce data transmission bandwidth by compressing and transmitting video signals through existing display interfaces. By using Hardent's Video Electronics Standards Association (VESA) Display Stream Compression (DSC) Encoder IP, video signals can be compressed and transmitted through Synopsys' DesignWare MIPI DSI Host Controller IP. Synopsys' DesignWare MIPI DSI Host Controller IP is compliant to the latest MIPI specification v1.2. The Hardent VESA DSC Encoder IP is compliant with VESA DSC standard v1.1 and enables visually lossless video compression between the application processor and the display system inside the system-on-chip (SoC). Hardent's VESA DSC Encoder IP compresses and transports the video signal to one or more DSI streams utilizing Synopsys' DesignWare MIPI DSI Host Controller and MIPI D-PHY IP. "Electronics manufacturers leverage visually lossless compression to enable compelling displays for ultra-high-definition mobile applications," said Alain Legault, vice president of IP products at Hardent. "We have collaborated with Synopsys, the industry's trusted provider of high-quality IP, to provide a fully interoperable solution that will allow companies to deliver next-generation displays." "The evolution of displays in mobile device...