Date: 16th Jun 2011
Toshiba developed time-to-digital converter
with interpolation circuits to reduce phase-noise
To cut the phase noise in Digital PLLs designed using
time-to-digital converter (TDC) functional blocks, Toshiba
has developed a new TDC integrating interpolation circuits
that use a low resistance conductor to connect the output
of two inverters. Toshiba claims a triple interpolation
splits the cycle of output signal of frequency synthesizers
resulting in reduction of phase noise by 90 percent, which
in turn reduce jitter in RF signals. This technology enables
to further migrate to high-speed wireless communication
chips for wireless LAN and WiMAX.
Due to simplicity of designing digital PLLs, the semiconductor
industry is now opting for digital PLLs instead of analog
PLLs. The drawback of digital PLLs are, they increase phase
noise, a degrading displacement in the pulse of a radio
frequency signal due to larger delay in the TDC's inverter
circuits. Cutting phase noise is essential for high speed
communication standards, like WiMAX, which require highly
accurate signals. This new Toshiba's solution utilizes a
stable waveform from the PLL itself as a reference time
interval for converting time to digital data, not the delay
time of the inverters.
In a test chip manufactured by Toshiba with 65nm CMOS process,
phase noise was reduced to -104dBc/Hz, 90 percent lower
than that of the previous all digital PLL that Toshiba announced
at ISSCC2011. Chip size was cut to 0.18 mm2, approximately
80 percent smaller than the analog PLL in a mobile WiMAX
transceiver chip that Toshiba announced at ISSCC2010.
This has announced this development on June 16 at the 2011
VLSI Symposium held in Kyoto, Japan.
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