Panasonic has achieved a conversion efficiency of 25.6% is in its crystalline silicon-based solar PV cell development, breaking its own previous record of 24.7 %. This achievement is at research level, where Panasonic has used heterojuntion technology to improve conversion efficiency. Panasonic has placed electrodes on the back of the solar cell to improve efficiency. The other technologies used in this achievement is explained below by Panasonic:
1. Reduction in recombination loss
A key feature of HIT technology is its ability to reduce the recombination loss of charge carriers, particles of electricity generated by light, through laminating layers of high-quality amorphous silicon on the surface of the monocrystalline silicon substrate, where power is generated. By utilizing the technology to form a high-quality amorphous silicon film on the monocrystalline substrate while minimizing damage to the surface of the substrate, it has been possible to realize a high temperature coefficient of -0.25% per degree Celsius which is able to maintain a high conversion efficiency even with high open circuit voltage (Voc) and at high temperatures.
2. Reduction in optical loss
In order to increase the current in a solar cell, it is necessary to lead the sunlight which arrive at the cell's surface to the monocrystalline silicon substrate, which is the layer which generates the power with less loss. Placing the electrodes on the reverse as back contacts allows the light to reach the substrate more efficiently. This has led to a marked improvement in short circuit current density (Jsc) to 41.8mA/cm² over Panasonic's previous figure of 39.5mA/cm² (in the case of a cell with a conversion efficiency of 24.7%).
3. Minimizing resistance loss
In solar cells, the generated electrical current is accumulated in the surface grid electrodes and output externally. Previously, the grid electrodes on the light-receiving side were optimized by balancing the thickness of the grid electrodes (thinning the grid electrodes to reduce the amount of light blocked) and the reduction of electrical resistance loss, but by placing the electrodes on the reverse side, it has become possible to reduce the resistive loss when the current is fed to the grid electrodes. In addition, a high fill factor (FF) of 0.827, has been achieved, even at a practical cell size by improving resistance loss in the amorphous silicon layer.
Cell propertiesOpen-circuit voltage (Voc)*9 0.740 V
Short circuit current (Isc)*12 6.01 A
Short circuit current density (Jsc)*12 41.8 mA/cm²
Fill factor (FF)*13 0.827
Cell conversion efficiency 25.6%
Cell area*3 143.7 cm²