First functional monolithic CFET demonstrated by imec at IEEE VLSI event

Semiconductor researcher imec presented for the first time electrically functional CMOS CFET devices with stacked bottom and top source/drain contacts at the 2024 IEEE Symposium on VLSI Technology & Circuits (2024 VLSI) held this week. While the results were obtained with both contacts patterned from the frontside, imec also shows the feasibility of moving bottom contact formation to the wafer backside – significantly improving top device survival rate from 11% to 79%. Imec’s logic technology roadmap envisions the introduction of complementary FETs (CFETs) in A7 node device architectures. When complemented with advanced routing techniques, CFETs promise to reduce standard cell track heights from 5T to 4T and even below, without performance degradation. Among the different approaches to integrate n- and pMOS vertically stacked structures, monolithic integration is considered the least disruptive compared to existing nanosheet-type process flows. At the 2024 VLSI Symposium, imec demonstrates for the first time functional monolithic CMOS CFET devices with stacked top and bottom contacts. The CFETs were integrated at 18nm gate length, 60nm gate pitch and 50nm vertical separation between n and p devices. Electrical functionality was demonstrated on a test vehicle with nFET and pFET devices using a common gate, and top and bottom contacts connected from the frontside. The pr...