Imec achieves Cu interconnect pitch of 2µm die-to-wafer hybrid bonding

At the 2024 IEEE Electronic Components and Technology Conference (ECTC), imec presented a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such fine-grained die-to-wafer interconnects pave the way to logic/memory-on-logic and memory-on-memory applications. On the longer term, die-to-wafer bonding will enable also die and wafer level optical interconnects, for which imec demonstrated a first proof of concept at ECTC2024. Imec is developing a process flow for direct die-to-wafer hybrid bonding at interconnect pad pitches well below 10µm, down to 1µm. To reach these goals, imec achieved a major process improvement, in particular preserving ultraclean surfaces during processing, die singulation and pick-and-place; and maintaining a high throughput during all the process steps. This has led to a first demonstration with a Cu bond pad pitch scaling down to 2µm. Hybrid bonding requires very high-quality surface preparation to achieve smooth surfaces with minimal Cu pad recess (<2.5nm), requiring careful optimization of the chemical-mechanical polishing (CMP) step of the Cu/SiCN surface. These properties need to be maintained during wafer singulation and die-to-wafer placement. To achieve a high-quality die singulation, without particles and impact to the Cu/S...