Heterogenous SoC design: Chiplet architecture design: Use open-source EDA tool-chain RapidChiplet

With the Moore's Law slowing and no-more offering lowering of cost per transistor designing, chip industry is migrating to heterogenous integration of separate silicon pieces on a silicon interposer. A new chiplet architectures has emerged as a promising solution. Offering heterogeneity, modularity, and cost-effectiveness, chiplets present a viable alternative. However, the vast design space of chiplet architectures poses significant exploration challenges. To address this, a team of researchers Patrick Iff, Benigna Bruggmann, Maciej Besta, Luca Benini, and Torsten Hoefler have developed an open-source EDA toolchain called RapidChiplet designed for rapid design space exploration of chiplet architectures. This toolchain provides fast estimates for critical metrics, enabling designers to efficiently navigate the complexities of chiplet design.
Pic above: Traffic types and paths within each type. Source: arxiv RapidChiplet utilizes a unified input format to estimate various metrics, including area, power consumption, thermal stability, manufacturing cost, latency, and throughput of inter-chiplet interconnects. This streamlined approach facilitates comprehensive analysis within a single framework. Leveraging advanced algorithms, RapidChiplet delivers rapid computation of design me...