CXL Consortium released CXL 3.1 specs

CXL Consortium released the Compute Express Link (CXL) 3.1 specification with improved fabric manageability to take CXL beyond the rack and enable disaggregated systems. The CXL 3.1 Specification improved to support optimization of resource utilization, creation of trusted compute environments as needed, extend memory sharing and pooling to avoid stranded memory, and facilitating memory sharing between accelerators. “The CXL 3.1 specification incorporates new features requested by the CXL community to create disaggregated systems and keep up with high-performance computational workloads,” said Larrie Carr, CXL Consortium President. “With the support of our members, we continue to develop and promote CXL technology to enable an interoperable ecosystem of heterogeneous memory and computing solutions.” Highlights of the CXL 3.1 specification feature CXL Fabric improvements and extensions Fabric Decode/Routing requirements Fabric Manager API definition for PBR (Port Based Routing) Switch Host-to-host communication with Global Integrated Memory (GIM) concept Direct P2P CXL.mem support through PBR Switches Trusted-Execution-Environment Security Protocol (TSP) Memory Expander Improvements Extended Meta Data with support for up to 32-bits per cache line of host specific state Improved visibility into CXL...