3nm chip design signoff: Equivalent to scaling of mount Everest!

Date: 17/10/2023
All the way from 180 nm to today's 3 nm, semiconductor chip designers continuously see one constant of growing design complexity. The climbing of this complexity mountain is getting steeper and steeper. At the nodes of 3 nm, the rate of rise of complexity looks to be lot more exponential than the previous nodes. If you apply the probability and information theory to the rate of rising number of bugs in today's semiconductor chips, both theoretically and practically taping out a successful chip is extremely difficult. So this process of signing off of chip design data fully ready for tape out before handing over to fab is becoming very tough task for the chip design team.

At the recently concluded Synopsys Signoff Confererence 2023 held in Bangalore on October 12, 2023, the experts from Synopsys and invited speakers were helping/sharing to attendees of this event by presenting with latest solutions, and also on the today's AI/ML supported industry trend in signoff process.

There were two tracks:

1. Timing and Power Signoff to explore latest technology advancements in constraints methodology, timing & power analysis and ECO convergence.
2. Extraction and Physical Verification Signoff focusing on the latest innovations in DRC, LVS, RC extraction, power devices, and ESD areas.

The keynote speakers:
Shankar Krishnamoorthy, General Manager, EDA Group, Synopsys and
Umesh Nair, Senior Director, Design Engineering, AMD.

Although AI/ML solutions are parallelly emerging along with the growing complexity to substitute a little bit of human thinking inside the chip design process. However still yet no significantly beneficial standalone AI tool has emerged in the signoff process.

The growth of complex design data is as exponentially rising as number of transistors in the chip are rising, and so is the massive growth of corners and the growing modelling complexity. Joining this complexity is achieving ultra low voltage accuracy, thermal analysis, glitch aware power analysis. In case of heterogeneous chiplet based multi-die, a different set of challenges arise. The multi-die demands power integrity electromagnetic/IR analysis, thermal-mechanical integrity analysis, signal integrity, extraction, DRC/LVS analysis of little different dimensions compared to monolithic.

Signoff


Well, this is about the physical design verification complexity. The marketing team of semiconductor companies, never want to compromise on the high-performance specifications they have fixed, irrespective of the development challenges.

At this early stage of AI/ML solutions in the chip design domain, there is no other alternative solutions other than AI/ML based solutions are seen for handling both the repetitive tasks as well as applying humanlike intelligence to the data as well as decision-making stages in the chip design process.

Below were the track-titles at the event:
1. Gain Higher Design Confidence and Designer Productivity with End-to-End Timing by Naveen Battu - Synopsys

2. Tutorial: Accelerate Physical Verification Closure with Synopsys IC Validator by Srinivas Velivala - Synopsys.

3. Left Shift of Constraints Development and Validation With TCM by Ashis Maitra - Intel

4. Driving Signoff Full chip DRC closure using IC Validator Flow at Advanced Technology Nodes by Sunil Kharate, Dinesh Londhe - Seagate.

5. Accelerating Last-Mile Design Closure with Synopsys PrimeClosure by Rajesh Gupta - Synopsys

6. IC Validator as a Comprehensive Physical Verification Solution by Sanjay U - Alphawave Semi

7. Tutorial: Accelerating Design Closure with Synopsys StarRC by Nishanth Babu Sana - Synopsys

8. Timing Robustness Prognosis for Potential Process Shift using PrimeShield SPICE2Design by Divyeshkumar Vora - Arm

9. Unlocking the Potential: Multi-Die and 3DIC Design Extraction using Synopsys StarRC by Prashant Mathur - Intel

10. PT-Si-HyperScale Deployment on Large Design with MiMs using Different Clock Sources by Sudarshan Chandak - Broadcom

11. Accelerating Turnaround Time: StarRC Parasitic Exraction for Arm Cores by Veena Venugopalan - Arm

12. System to Silicon: Synopsys Low-Power Solution by Sandeep Aggarwal - Synopsys.

13. StarRC Parasitic Explorer Deployment and Usages for PEX UnitQA by Amar Kumar Yadav - Samsung

14. Challenges of Power Estimation for Purpose Built MCU / MPU by Sayandeep Nag - NXP Semiconductors

15. Silicon Frontline Tutorial: Improving Design ESD Robustness with Full Chip CDM Simulation by Srinivas Velivala - Synopsys

Synopsys is trying to bring in AI/ML elements in most of its tools. Some of its popular signoff tools include:

Timing and ECO Closure: PrimeTime, PrimeClosure and PrimeShield.

Synopsys NanoTime is the golden timing signoff solution integrating with Synopsysí PrimeTime for transistor-level design for CPU datapaths, embedded memories and complex AMS IP blocks.

Power and Power-Integrity Closure: PrimePower, and RedHawk Analysis Fusion

Library Characterization: SiliconSmart and PrimeLib

Parasitic Modeling and Extraction: StarRC, and QuickCap NX

More data can be found at: https://www.synopsys.com/implementation-and-signoff/signoff.html

Author: Srinivasa Reddy N
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