3nm chip design signoff: Equivalent to scaling of mount Everest!

All the way from 180 nm to today's 3 nm, semiconductor chip designers continuously see one constant of growing design complexity. The climbing of this complexity mountain is getting steeper and steeper. At the nodes of 3 nm, the rate of rise of complexity looks to be lot more exponential than the previous nodes. If you apply the probability and information theory to the rate of rising number of bugs in today's semiconductor chips, both theoretically and practically taping out a successful chip is extremely difficult. So this process of signing off of chip design data fully ready for tape out before handing over to fab is becoming very tough task for the chip design team. At the recently concluded Synopsys Signoff Confererence 2023 held in Bangalore on October 12, 2023, the experts from Synopsys and invited speakers were helping/sharing to attendees of this event by presenting with latest solutions, and also on today's AI/ML supported industry trend in signoff process. There were two tracks: 1. Timing and Power Signoff to explore latest technology advancements in constraints methodology, timing & power analysis and ECO convergence. 2. Extraction and Physical Verification Signoff focusing on the latest innovations in DRC, LVS, RC extraction, power devices, and ESD areas. The keynote speakers: Shankar Krishnamoorthy, General Manager, EDA Group, Synopsys and Um...