Accellera announces release of PSS 2.1 to improve chip design automation

Date: 17/10/2023
After a bit gap Accellera Systems Initiative has approved the latest Portable Test and Stimulus Standard (PSS) 2.1., which can be downloaded from

“Industry adoption of the PSS standard continues to rise across the globe as new features are added to help increase productivity,” stated Lu Dai, Accellera Chair. “It is our mission to deliver standards that help to improve the design automation process, and PSS 2.1 brings even more productivity and usability to the system-level design and verification community.”

PSS benefits:
Reduced test development costs with portability and rapid creation of complex tests, describe and share SOC configuration Inter-IP initialisation and power sequencing at high-level, enables effective communication through its semantics and constructs, better post silicon bring up and validation. Understanding every detail of SOC is not required with PSS partial scenario specifications.

PSS supports creating a single representation of stimulus and test scenarios, usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of scenarios that run on a variety of execution platforms, including simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify intent once and observe consistent behavior across multiple implementations.

“I am very proud of our dedicated working group members as we continue to develop the standard and bring even more flexibility and new capabilities to our user community. We have made significant advances with PSS 2.1, including new features that collectively enhance the versatility and efficiency of PSS to advance and simplify modern electronic system verification,” stated Tom Fitzpatrick, Vice Chair of the Portable Stimulus Working Group. “We welcome feedback from the community as we continue to develop the standard.”

Additions to PSS 2.1:
The update to the standard focuses on modeling and usability, with the introduction of many significant features aimed at enhancing its capabilities for efficient hardware and software verification.

These additions include:
Support for floating-point data types and associated math functions, which broaden the scope of verifiable designs
Enhanced capabilities for interaction with memory management via features for implementing custom address translation and querying the source address region of allocated memory
Enabling more flexible generation of random data via support for randomizing the contents of lists, performing constrained randomization in exec blocks and functions, and specifying distribution weights
Providing core library support for emitting formatted text and messages, operating on files, and error reporting

PSS 2.1 also simplifies the description of common modeling tasks, such as accessing individual register fields, capturing conditionally-compiled content, limiting the impact of inferred actions on an activity region, and specifying pool binding with arrays of components. The standard also expands the capabilities of packed structs, with support for Boolean fields and explicitly-sized enum-type fields, and adds support for static functions in component contexts.

A list of the new features added to the latest release can be found in the introduction to the standard.

More Information and Background on Portable Stimulus:

Accellera has resources available to learn more about portable stimulus and how it can positively impact your design and verification methodology. Members of the working group presented a tutorial, “User Experiences with the Portable Stimulus Standard,” during DVCon U.S. 2023. Additional information is available on the Portable Stimulus Working Group page. Feedback on the standard can also be provided through the Portable Stimulus Community Forum.

News Source: Accellera