DVCON India 2023: Chip design verification in AI driven 3nm EDA era

Date: 21/09/2023
DVCON India, an annual chip design and verification event conducted in Bangalore, India evolving as must attend event for chip design engineers who are deeply into verification and testing of chips. This year's AI/ML focused DVCON India 2023 was well attended by mix of both professional working engineers as well as students aspiring to take up career in VLSI domain.


Pic above: Increased women presence at the event

Whether you call it artificial intelligence or advanced high-performance computing, VLSI chip design industry is fully relied on design automation software which uses most innovative software algorithms to save the chip designer from huge number of repeating tasks, create virtual model of physical and electrical representation of Integrated Circuit behaving exactly like the real chip. Tools also process huge amount of chip design data automatically using dedicated chip design software. It is comparable to virtual design of massive cities so that automated robots can built city in couple of years. Here in case of semiconductor chip manufacturing, the robots are basically semiconductor manufacturing equipment baking three-dimensional silicon structures. While the civil-engineering infrastructure uses bricks, sand and cement, semiconductor integrated circuits use transistors, insulators and copper as key materials. The most modern 3 nm chip packs around 190 million transistors in square mm and 10s KMs of copper wires. So the concept of digital twin is very well happening in VLSI chip design from decades.

As part of test and verification process, the chip development teams need to check each transistor whether its functioning as it is supposed to do. You need a massive scale of automation to check 10s of billions of transistors. It's impossible to check without automation tools but still you need a thoroughly educated electrical and electronics engineering expert at each stage of test and verification, to analyse data and approve for a pass.

What called as EDA 3.0 version of automation tools worked quite well up to 14nm, however for chips made at lower than 7nm nodes, the time to market pressure is so huge, you got to tape-out the chip with in the short window of market opportunity for the successful commercial launch of the systems based on these chips. VLSI verification engineers are under severe pressure to functionally verify each IP block and each line of the code so that chip is made bug free. We could easily see at the DVCON India event, highly experienced verification engineers are desperately looking for AI/ML based advanced software tools to assist them to verify massive scale of data in shorter timeframe.

This trend offers a huge market opportunity for EDA vendors in developing AI-based advance EDA tools to support today's market requirements. All the three top leading EDA vendors namely Synopsys, Cadence, Siemens are fully leveraging their domain expertise and the emerging AI software technologies such as generative AI in offering advanced AI EDA tools at each stage of chip design and verification. Few of these tools are already successful commercially, but not all the tools are that effective due to lack of machine learning data particularly for generative AI type of tools.

These tools are engaged to save development time with lesser number of engineers and to catch the bug, at the same time users of these tools expect them to be very reliable, accurate and effective.

With AI-driven and AI-assisted automation tools already available in production-grade, these tools are getting connected with each other for improved automation levels. We can expect higher level of automation in coming years.

Since I got to attend another important event on electronics manufacturing happening at a far away place in Bangalore from where this event was conducted, I could attend first-four keynotes on the first day. Here is my observations and key trends I share in this article:

Verification expert Sandeep Mehrotra, Vice President of Engineering, Synopsys, started the session with his key note titled "Autonomous Verification: Are we there yet?". In my previous article, I have already covered his talk in the article titled "Trusted AI EDA is the way out in the maze of 3nm chip design and verification"

The second speaker Abhi Kolpekwar, VP & General Manager, Siemens EDA presented a keynote titled "Smart Verification: Faster is not enough!" He started off by comparing AI role on EDA and general data processing to electric energy role on industrial revolution.


Pic above: Rising failures in first silicon success

Abhi's talk highlights: There is 23% decline in first silicon success since 2014. Developments of semiconductors is becoming a source crunch, where ASIC design starts are rising at 5% CAGR from 2015 to 2023, engineering man-months is around close to 40,000 for a 3nm chip design, where it has increased more than 100% compared to 7 nm designs. The cost share of semiconductor in electronics products is also rising to 30%. This calls for EDA 4.0 where AI and ML based data analytics are essential.

There is a need of resource scalability, collaborative data driven solutions and predictive analytics with deep insights into data.

P R Sivakumar, Founder & CEO, Maven Silicon presented keynote titled "Journeying Beyond AI: Unleashing the Art of Verification". Siva delved into how the semiconductor industry runs by explaining the complete semiconductor ecosystem from IP vendors to fabs to design teams in India, clearly pointing the semiconductor industry is a global industry with each region playing a role. He calls verification an 'art'. He explained how the combination of AI and cloud computing enabling AI-driven semiconductor industry. He is also a RISC V open ISA expert, where he alerted how risky if chip designer go without RISC V in their designs.

He shared a slide how chip design costs are rising as the design move from 14 nm to 5nm nodes. From around 100 million to design a 14 nm chip to around 500+ million to design a 5 nm chip. The verification costs alone is in the range of 100 million dollars for a 5 nm design.


Pic above: Growing chip development costs

With around 76% of ASICs requiring two or more respins, where more than 50% of time logic or functional flaws remain the leading cause of ASIC re-spins and design errors and the leading cause of functional flaws. All this causing 66% ASIC design projects falling behind schedule, where around 60% project time spent on verification. He also shared a research data where 47% of ASIC verification engineers time spent on test planning, 21% on creating test and running simulation and 18% on test bench development and the rest on debug and other activities.

He finds AI in design verification can help in creating test cases, code and functional coverage, formal verification, performance analysis and bugs. Generative AI can be used in RTL/TB source code generation.

Dr. Ziyad Hanna, Corporate Vice President & R&D GM Israel, Cadence Design Systems talked on how DV community to accelerate research, development and deployment of AI and Generative AI solutions with title "AI for Chip Design: Scaling DV Capacity to Meet Massive Demand Growth"

Ziyad highlighted productivity challenges in chip design with rising complexity, more and more chip design starts and not enough engineers in this domain. AI driven system design solution looks to be the only path for these challenges. He explained how Cadence Verisium employs AI in various steps of verification. He presented a slide showing how Cadence' Xcellium enhance simulation performance by using a lesser regression CPU cycles. He also makes a point on how formal verification technology enhanced by AI.


Pic above: Cadence AI-driven verification solutions

Another interesting keynote titled "Bugs, Transistors, Chips, and Waves A Panoramic View of the Journey from Four to a Quintillion, and Beyond" was presented by Vishwanath Ananthakrishnan, SVP & GM, Hardware Engineering, Mirafra Technologies. He ran through the slides showing the history Of semiconductor chip development, to how does the world looks like in the year 2073 in terms of using electronic gadgets displaying autonomous flying cars to quantum computers to life on planet Mars.


Pic above: Gadget world in 2073

Though the present EDA industry address mega chip design challenges, the advanced 3D chiplet based nano-devices fabrication equipment needs tools to automate physical inspection and verification, this gives an opportunity for new companies in EDA domain to spring up. One such company called Sandbox launched user-friendly, domain-specific software solutions for semiconductor manufacturing industry. More on this company in my next article.

Author: Srinivasa Reddy N
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