Trusted AI EDA is the way out in the maze of 3nm chip design and verification
Date: 15/09/2023
DVCON India 2023 held in Bangalore exclusively for chip design and verification was successfully concluded on 14th Sept 2023. In trend with growing interest in using AI/ML in chip design verification, significant amount of talks and discussions were focused on growing challenges in 5nm and 3nm chip design and addressing them through fast evolving AI/ML driven and assisted EDA tools.
Though the generative AI is giving semi-automated solutions for maze of issues, it's getting hallucinated quite often as its fed with queries for automated responses for critical challenges, however is showing explorable way to some extent, provided the user has deep domain expertise.
EDA vendors are putting significant investment in these areas and coming out with production ready AI powered latest tools to address some parts of challenges.
Verification expert Sandeep Mehrotra, Vice President of Engineering, Synopsys. Started the session with his key note titled "Autonomous Verification: Are we there yet?"
Pic above: Slide on factors driving the autonomous verification
Here are the highlights from his keynote:
In adopting AI-based automation, EDA can follow how vehicle driving automation such as ADAS, where step-by-step increasing of automation is being followed, initially with more human interface, and towards step by step full automation wherever it is 100% safe and reliable.
Automation in verification is required due to extreme growth of complexities and issues in 5nm and 3nm, where shorter time to market is the main pressure for choosing further automation in verification.
Around 70% of time in verification is spent on debug and coverage, Sandeep explained how various stages of debugging can be automated by using AI/ML automation techniques. Machine learning can help in coverage part of VLSI verification.
AI-assisted debug flow, AI-assisted check-in insights, AI-driven controlled regression, AI-driven Triage, AI-assisted RCA are now possible. Voice-based instruction to debugger and any such voice-based instructions is also a take now.
Future looks pretty AI dependent, where simple human English-language specs can be translated into machine-readable specs using generative AI.
First time tape-out success is very tough to achieve and respins are costly. So only way is to reduce respins and reduce design time by going for further automation.
Synopsys AI powered VSO.ai verification tool delivered benefits such as 10 to 15% higher coverage in case of automotive and 26% higher coverage in case of IP provider, 2X reduction in processor tests, and 68% reduction in smart phone SoC tests, claimed in the slide by Sandeep.
Pic above: Slide on Root Cause Analysis benefits
Lack of data is a big concern in some of the areas causing hallucinations to generative AI tools. There are still many areas where AI/ML cannot be applied as of now.
So at this stage partial automation using AI tools is highly feasible and industry is fast moving into next phase.
When I asked him about training engineering students for the present-day requirements of AI ML-based chip design, he said that is a very important one, they should be informed and educated about present and future industry's requirements along with the availability of tools.
Pic above: Slide on RTL Copilot tool providing SystemVerilog code for natural langauge text.
This one is a quick article from the event, I will cover in detail my interaction with other service providers, tools vendors and experts whom I met at DVCON India 2023 in my next articles.
Author: Srinivasa Reddy N
