DAC 2023: AI by AI to design heterogenous 3D IC
Date: 16/07/2023
60th version of Design Automation Conference (DAC), the most popular event for electronics and semiconductor design automation concluded on 13th July 2023. Host of cutting-edge technologies in electronic design automation discussed and displayed. It was reported by many attendees that this year event was buzzing with packed halls with EDA geeks and semiconductor nerds.
Though AI was the centerpiece of discussion at this year's DAC, the event also gave importance to digital-twin, open source tools and IP, and other issues only EDA industry can understand. EDA industry which is also referred as Electronic System Design (ESD) industry generated a revenue of $3,951.1 million in the first quarter of 2023, up by 12% from $3,527.7 million in the first quarter of 2022, as per the latest finding from ESD Alliance.
AI is both a market opportunity as well as internal change-driving tool for EDA companies to sell latest EDA software tools to develop AI chips, and turn their EDA software into AI based. We got to see whether they can generate huge profits out of AI, what they used to with traditional place and route tools and design reuse tools.
AI is changing the design and development of next generation chips. AI is used for place and route and optimize IP block placements where the AI algorithms help in continuously iterate and learn from patterns and optimize design layout. AI is also playing role in micro-architecture designs.
As the realization of digital twins getting closer and closer, it’s kind of bringing semiconductor equipment manufacturing and EDA tool vendor closer and closer. We still don't know whether it's collaboration or competition. Since this year's DAC event was co-hosted along with Semicon West, tells more about how close semiconductor equipment manufacturing and EDA tools are getting.
Lot more simulation-based software requirements in the growing market of heterogeneous integration based 3-D IC fabrication. Lot more physics and nano-mechanical engineering related software automation and the integration of those tools with electronics design tools is required for 3-D chiplet based IC manufacturing. When it comes to EDA software tools for 3D-IC fabrication, the industry is running short of what is really required. There are still many missing elements for smooth and reliable flow. Please note the EDA industry requirements, when it comes to reliability is very high.
At the event in a panel discussion, Joe Costello and Wally Rhines recounted their experience of running EDA companies. Joe Costello was instrumental in the success of Cadence where as Wally Rhines was for Mentor Graphics which is now part of Siemens.
Here are some more observations from this year's DAC:
Caliptra, an industry-first open-source collaboration of an integrated silicon root of trust IP for datacenter peripherals introduced opensource RoT project, a result of collaboration among industry leaders AMD , Microsoft, nvidia, and Google.
Dave Kelf from BrekerSystems talked about how verification is changing to meet chiplet requirements. Bob Smith and Dave talked on chiplets and new verification requirements.
RISC V: Micro Magic demonstrated the World Fastest and Most Power Efficient RISC-V. Codasip was at the event to help SOC designers customise RISC V based processors using company’s innovative EDA toolset, Codasip Studio. CHIPSAlliance is working to build a strong open source hardware ecosystem comprised of IP, design, EDA & PDKs. Imperas and Ventana were also at event supporting RISC V based designs.
Cast Inc was there at DAC to help find IP core solutions for your current SoC designs.
1000 plus RISC V cores in neural processor is norm and the norm soon to be 10,000 cores in a chip. For this kind of density, new chip architectures are explored. Esperanto AI inference chip with 1000 RISC cores consumes 25 Watts. Wally Rhines of Cornami calling it as Tsunami of processor cores and the Cornami, where he is part of is named so to mean core-Tsunami.
Marco Meuli from STMicroelectronics won the 60DAC Poster Gladiator competition with his presentation, 'Requirement Tracing for Design Flow in Communication Protocols IP.'
Silicon Interfaces presented at the 60th DAC Design Automation Conference Paper titled "Low Power and Area Efficient 64 Bit Vedic Multiplier Design for High Speed Operation in ASIC-DSP Applications". It’s founder Subhas Basu quoted "The 60th DAC is landmark/watershed event as it has brought implementation and application of Artificial Intelligence and Machine Learning to the fore along with open source multi-Core usage and to this extent it has been the seeding ground for AI/ML for Simulation and Fault Simulation and of course, demonstrating the use of Vedic Arithmetic Logic Units (ALUs) to speed up processing. With geometries for manufacturing hitting low bounds, any way to speed up computation, lower power usage and of course area, is a game changer and disruptive. The future is being written now and its all happening at the 60th DAC".
Synopsys EDA Group in collaboration with Georgia Tech were honored at DAC with the prestigious Design Automation Conference (DAC) Best Paper Award. Their paper, “RL-CCD: Concurrent Clock and Data Optimization Using Attention-Based Self-Supervised Reinforcement Learning,” was the culmination of six months of collaborative research into methods to drive concurrent clock and data-path (CCD) optimization in physical design.
Agnisys demonstrated innovative register info management system to capture HW functionality + addressable register map in single "executable" spec.
Mirabilis Design was at the event where it showcased its VisualSim Architect, a general purpose modeling and simulation software application that can be used to build graphical models, run simulations and generate reports. Deepak Shankar, one of the co-founder at Mirabilis said "In the case of the DAC Youth and Poster session, the focus was on quantum computing. A lot of interesting concepts using heuristics and SAT algorithms. The audience that attended were serious folks that had specific problems. As an exhibitor it really helped me focus on the real application and offer a real solution."
China based EDA company Easy-Logic Technology showcased its latest Functional ECO features at DAC 2023, including its newly released product ScanChainECO, which is designed to address Design-For-Test (DFT) issues during the functional ECO process.
To go bit outside DAC event but on the trend of AI in chip design, Lisa Su, CEO of AMD sees AI to dominate the chip design industry. Recently she spoke at 2023 World Artificial Intelligence Conference (WAIC) in Shanghai. She said AI is better option for testing and verification of chips. She suggested interdisciplinary collaboration in electronics hardware design including semiconductor chips. She finds generative AI to play more role in designing future chips.
Author: Srinivasa Reddy N
