Samsung foundry supported by Cadence 3D IC EDA tool

Samsung semiconductor foundry customers can now use 3D IC design tool Integrity 3D-IC platform from Cadence for developing chips with multiple dies. Integrity 3D-IC platform supports Samsung’s new system description language called 3D CODE standard to achieve smooth flow and interoperability. Latest reference flows and corresponding package design kits are provided based on the Cadence Integrity 3D-IC platform . This tool is claimed as industry’s only unified platform that includes system planning, packaging and system-level analysis in a single application interface. Integration, performance and reliability issues such as multi-die designs, productivity and reducing design turnaround time, flow complexities, configuration challenges, and system-level thermal and power integrity issues are addressed in this Cadence latest unified solution. Integrity 3D-IC platform features early analysis for the power delivery network (PDN), thermal and system-level layout versus schematic (LVS) and design rule checking (DRC). Cadence has incorporated in this flow it's Cadence Allegro X packaging technologies, multiphysics system-level analysis tools such as Celsius Thermal Solver and Clarity 3D Solver. “Customers creating high-performance designs are looking to make use of the benefits advanced packaging technologies offer, such as lower power, lower yield cost and system perform...