Samsung IP eco supported by EDA Cos Cadence and Synopsys

While the node shrinks from 5 nm to 3 nm, VLSI design data growth gets compounded and complexity grows in Giga range in terms of data, testing, verification, and number of functions and variables. So it's not just partnering with semiconductor/electronics design automation firms, nearly co-working, co-executing with interdisciplinary experts working in sync across semiconductor engineering, software design tools, Silicon IP experts, and mutually accepted standards stakeholders. To keep IP risk-free and to ensure successful first tape-out of chips EDA firms Synopsys and Cadence are closely collaborating with Samsung foundry to ensure best support for common customers. In a separate releases both Synopsys and Cadence have announced delivering silicon VLSI IP for advanced nodes of Samsung's semiconductor foundry.
Synopsys to enhance its IP offering for Samsung's advanced 8LPU, SF5, SF4 and SF3 processes and includes Foundation IP, USB, PCI Express, 112G Ethernet, UCIe, LPDDR, DDR, MIPI and more. Synopsys said it will also optimize IP for Samsung's SF5A and SF4A automotive process nodes to meet stringent Grade 1 or Grade 2 temperature and AEC-Q100 reliability requirements, enabling automotive chip designers to reduce their design effort and accelerate AEC-Q100 qualification. The auto-g...