CEA-Leti to Report Progress on 3D Interconnects for Wafer-Level Platforms
CEA-Leti will present seven papers on 3D interconnects focused primarily on semiconductor wafer-level platforms at the Electronic Components and Technology Conference (ECTC), May 30-June 2, in Orlando, Fla.
The institute is focusing on achieving high levels of heterogeneous integration of technologies and components on a host silicon wafer through high-density interconnections (fine pitch) to meet requirements of HPC/edge-AI chiplets, optical computing, displays and imagers. It offers a wide range of advanced, complementary technologies such as die-to-wafer and wafer-to-wafer bonding, whose interconnection densities are closely linked to TSVs to keep the densities for layer or ball-grid array (BGA) connections.
§ Advanced 3D Integration TSV and Flip-Chip Technologies Evaluation for the Packaging of a Mobile LiDAR 256-channel Beam Steering Device Designed for Autonomous Driving Application
§ Demonstration of a Wafer Level Face-To-Back (F2B) Fine Pitch Cu-Cu Hybrid Bonding with High Density TSV for 3D Integration Applications
§ Process Integration of Photonic Interposer for Chiplet-based 3D Systems
§ Integration and Process Challenges of Self-Assembly Applied to Die-to-Wafer Hybrid Bonding
§ Recent Progress in the Development of High-Density TSV for 3-Layer CMOS Image Sensors
§ 3D Silicon Interposer for Terabit/s Transceivers Based on High-Speed TSVs
§ Characterizations of Indium Interconnects for 3D Quantum Assemblies
CEA-Leti’s Stéphane Bernabé will co-chair the special session on Photonics Packaging, May 30 at 1:30 – 3:00 p.m.
In addition, a Best Poster award from ECTC 2022 will be awarded to Aurélia Plihon et al, for their poster: “Scalable Through Mold Interconnection Realization for Advanced Fan-Out Wafer-Level Packaging Applications”.
CEA-Leti experts will be onsite at booth 234 and available to discuss the findings in the presentations.
Author: Srinivasa Reddy N