Chiplet-driven, More-than-Moore way creating exponential growth for semiconductor packaging

While the monolithic semiconductor chips getting denser and denser with the Moore's law progressing towards 1 nm technology node, the cost of developing complete system on chip is alarmingly rising in the nodes of 3 nm and lower. It is estimated to cost around $ 750 million to design a monolithic SoC chip in the nodes of 2 nm. Although shrinking is achieved but some of the other benefits of Moore's Law are missing at <7nm nodes. So the better economic alternative is to go for heterogeneous integration of multiple monolithic semiconductor chips called chiplets in 3-dimensional semiconductor packaging and also using advanced interconnect technologies. In fact, chiplet-era already started by leading chip vendors Intel, Broadcom, Samsung and Micron, who have launched successful products in the market. Due to this major tech-driven shift from System-on-Chip to System-in-Pacakge, semiconductor packaging industry is estimated to grow faster than semiconductor chip fabrication. More and more semiconductor companies to offer their monolithic integrated circuit devices in the form of chiplets. The system designer of the end product to pick various chiplets for the targeted application, and outsource that design to semiconductor fabrication service provider to assemble and test the product....