HomeNewsNews Details
News Details
Date: 25-08-22

Intel semiconductor tiles era: Chiplets to constitute 1-trillion transistors sys-in-pack

At the IEEE hotchips event, Intel's CEO Pat Gelsinger shared to the audience Intel's way of designing 1-trillion transistor integrated circuits on semiconductor for new era of fast-growing AI computing.
It can go beyond personal computer and smart phone to metaverse, blockchain/Bitcoin, edge computing, HPC/AI datacentre, automotive computing for autonomous driving, and many such emerging applications that automate and smart everything.  

It can be a single tiny low power consuming chiplet for your edge computing, to a lot bigger ultrahigh performance system of chips packing trillions transistors for supercomputing datacenters,  and even  a  unique low-power system of chips for AR/VR kind of applications powering metaverse. Chiplet based system in package is emerging as better option than monolithic chips. The new advances in chip packaging is driving this trend.

The market opportunities to expand for such heterogeneous semiconductor chips.  Customization of silicon is also a driver of this market. Gamer processor can have a set of graphic-processing focused  different chiplets compared to notebook processor used by business executive.

Below are the other key features, points, facts on Intel's new semiconductor technology roadmap available in the public domain and shared by Intel's executives including what Pat Gelsinger said at hotchips:

1. This highly scalable solution feature high speed interconnect, high bandwidth memory, dense FPGA fabric, high-speed external network interface, best of the digital, best of the analog, and best of the RF in a single package. Monolithic IC wafer chips are connected one next to the other using interposers or placed one above the other like 3-D structures and also mix of both. Semiconductor factories making such chips are called system foundry.

2. Chiplets can be from different process geometries and fabs/foundries, Intel to use TSMC made chiplets along with its own chips in its future tile solutions. Intel  looks to be open to source and use silicon wafer tiles from even other foundries and IDM companies.

3. 3-D system in package solution is more economical than building  everything on 3 nm single chip, however chiplet's made out of 3nm will be used wherever they are necessary, for high-performance low-power computing. System in package offers flexibility, customisation and supports low-volume demands.

4. This Lego like placement of chiplets is supported by the new standards for chiplet interfaces. A consortium called UCIe consortium is formed by Intel, TSMC, Samsung, ARM, Qualcomm, Advanced Semiconductor Engineering, Meta, Microsoft and AMD. UCIe consortium is providing Silicon die to die interconnect standard to promote open Chiplet ecosystem.

5. The market for chiplet based chips estimated around US$ 2 billion in 2021  and to reach around US$ 50 billion by 2031.

6. Intel's new personal computer chip products to be launched based on tiles concept is MeteorLake, ArrowLake and LunarLake. Separate CPU, GPU, SoC and I/O tiles stacked using Intel’s Foveros interconnect technology

7.Intel's  GPU Ponte Vecchio to process heavy computing  and AI supercomputing workloads is also  tiles-made using a combination of embedded multi-die interconnect bridge (EMIB) and Foveros packaging technology.

8.Xeon D-2700 and 1700 series processors for enterprise and cloud applications are also to be tile-based design using various advance  computer cores, high-speed Internet, packet processor, inline crypto acceleration, time coordinated computing (TCC), time-sensitive networking (TSN) and built-in optimization for AI processes.

9. Intel had acquired FPGA business of Altera, and plans to release new tile concept based FPGA chips having basic FPGA fabric, analog chiplets, and can have  hardened digital logic tiles and any such processing and networking related tiles.

10. Intel said it is also strengthening its software portfolio, which includes next-generation EDA tools for this kind of 3-D semiconductor system foundry.

Pat Gelsinger quote at the event: Combined with other advances like RibbonFET, PowerVia, High NA lithography and developments with 2.5D and 3D packaging, we have an aspiration to move from 100 billion transistors on a package today to 1 trillion by 2030. There has never been a better – or more important time – to be a technologist. We must all be ambassadors for the crucial role semiconductors play in life today

0 Comments
Default user
Related News