In this year of 2022, Samsung is first company to make 3 nm semiconductor chips ahead of TSMC. In the race of making densest chips, Samsung was left behind TSMC in 5 nm node race. However in the 3nm lap, Samsung leads the race by announcing first shipment of 3 nm chips from its V1 line in Hwaseong fab. 3nm GAA process made chips deliver 45% power saving , 23% improvement in performance, and 16% saving in space compared to Samsung's 5nm process. Samsung is also into development of 2nd gen 3nm process, offering power consumption reduction by up to 50%, improve performance by 30% and reduce area by 35% compared to its 5 nm chips.
Samsung has made the 3nm chips by using gate all around (GAA) technology and used nanosheets instead of nanowires. Samsung’s GAA Multi-Bridge-Channel FET (MBCFET) tech clears some of the hurdles faced using FinFET, where they enable IC chips to operate at lesser supply voltage levels and increase performance performance by rising drive current capability.
Samsung Electronics CEO and DS Division Director Kyehyun Kyung said “3nm GAA mass production is a landmark achievement for our foundry business: our early success in GAA technology as an alternative to FinFET transistors which have reached their technological limit is a prime example of true technological innovation, creating something from nothing.”
Samsung celebrated this first shipment by holding a commemorative ceremony with participation of ministers from South Korean government, Samsung's semiconductor technology partners and its fabless customers. Chang-Yang Lee, Minister of Trade, Industry and Energy stated “Samsung Electronics, the system semiconductor industry, and the material, parts, and equipment industries join hands to stay ahead of fierce global competition in ultra-fine processing.” He emphasized that “The government will spare no effort in supporting private investment, fostering talent, developing technology, and building ecosystems for material, parts, and equipment under the government’s ‘Semiconductor Superpower Strategy’ announced last week.”
CEO Hyun-deok Lee of Wonik IPS, a Korean semiconductor equipment company, attended the event: “Working with Samsung Electronics on preparations for 3nm GAA foundry process mass production has helped enhance the capacities of our personnel at Wonik IPS as well - we hope to continue collaborating closely with Samsung Electronics toward the advancement of Korea’s semiconductor equipment industry.”
CEO Jang-gyu Lee of Telechips, a Korean fabless company commented “Telechips has high expectations for use of Samsung Electronics’ ultra-fine processes in future product designs,” adding “Samsung Electronics has actively made available ultra-fine foundry processes to Korean fabless chip companies, providing a host of support measures to help fabless companies expand their product design scope.”
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”
Samsung's EDA software partners Ansys, Cadence, Siemens EDA, and Synopsys have praised Samsung's achievement and announced their tools support for Samsung' 3nm GAA chips.
Samsung said it has started research work on gate all-around transistor in early 2000s, where this tells they must be also working on the technology that can become mainstream in another 10 to 20 years.
High performance computing chips, and mobile phone SOC chips are the first products going to made using 3nm GAA nanosheet process.
Samsung also shared its expansion plan of 3nm GAA foundry process mass production from the Hwaseong Campus to to its another campus of Pyeongtaek in the coming years.
TSMC, Samsung's closest competitor in this race, has also announced in the month of the June 2022, that mass production of its 3 nm chips sometime before the end of 2022. Though officially not confirmed by TSMC, there are some media reports saying TSMC to produce its 3 nm chips from the month of September 2022. However TSMC still using FinFET for its 3 nm process. TSMC plans to use nanosheets in its 2 nm process nodes, whose production volumes scheduled to begin in 2025.
TSMC also disclosed in its release in the month of June that its chip-on-wafer and wafer-on-wafer 3D semiconductor fabrication using 5 nm node scheduled for 2023.
Both the TSMC and Samsung putting tens of billions of dollars into semiconductor research, so that they stay ahead of others including their closest competitor; Intel. Samsung also competes with SK Hynix, Micron and Kioxia in the semiconductor memory segment.
In another latest announcement by Samsung, company said its Key/top executives broke ground for building most advanced and massive semiconductor research facility in a area covering about 109,000 square meters within its Giheung campus. The total investment planned into this facility is KRW 20 trillion by 2028 (approximately US$ 15 billion).
“Our new state-of-the-art R&D complex will become a hub for innovation where the best research talent from around the world can come and grow together,” said President Kye Hyun Kyung, who also heads the Device Solutions (DS) Division. “We expect this new beginning will lay the foundation for sustainable growth of our semiconductor business.”