Standards CDC specs for SoC VLSI design

EDA IP standards organization Accellera Systems Initiative has formed a Proposed Working Group (PWG) to define a standard Clock Domain Crossing (CDC) collateral specification to simplify SOC VLSI design integration. It has also announced the first Proposed Working Group meeting to be held on Tuesday, September 13th from 9am – 4pm PT at Intel SC12, 3600 Juliette Lane, Santa Clara, SC12-538. VLSI engineers can register for this meeting. Non Accellera member companies can also attend this meeting. Leading VLSI chip design companies such as Arm, Cadence, Intel, Qualcomm, NVIDIA, NXP, STMicroelectronics and Siemens are involved in this program. “At Accellera, we create and deliver standards that enhance the design and verification productivity of electronic products,” stated Lu Dai, Chair of Accellera. “Our members elevate the need for standards that will be beneficial to their projects. Currently, collateral generated from different CDC verification tools are not interoperable with each other. Our new Clock Domain Crossing Standardization PWG aims to address this issue. We look forward to input from the community and encourage all interested companies to join the PWG and provide guidance on the need for a standard in this area.” “Typically, the CDC verification tools that the IP and SoC teams use rely on different formats to capture CDC intent,” stated Martin Barnasconi, ...