Applied' etch, deposit, test tech enables nm-shrinking of chips using EUV

Date: 05/05/2022
As the top-notch semiconductor fabrication industry picks up angstroms as units instead of nanometres, the difficulty in shrinking the size of transistor is reaching new heights. In such a situation only few companies able to successfully do research and development to make chips at nodes less than 2 nm.

Applied Materials supports two dimensional scaling with Extreme ultraviolet litho in fabricating 3D Gate-All-Around transistors. Although extreme ultraviolet (EUV) lithography enables to print smallest patterns on wafer, there are challenges on material deposition, etching and metrology.

Industry is trying to achieve scaling in all dimensions. With the classic Moore's Law 2-D scaling throwing a lot more challengers, chip industry has already pioneered a lot of technologies including backside power distribution networks and Gate-All-Around (GAA) transistors. Along with the improvement in power performance and area (PPA), cost and time-to-market factors getting added to this. So the PPA is becoming PPACt (power, performance, area, cost and time-to-market), as stated in a press release from Applied Materials.

“Applied’s strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV,” said Dr. Prabu Raja, Senior Vice President and General Manager of the Semiconductor Products Group at Applied Materials. “We are also detailing how GAA transistors will be manufactured in fundamentally different ways than today’s FinFET transistors, and how Applied is ready with the broadest product line for GAA manufacturing including new steps in epitaxy, atomic layer deposition and selective materials removal along with two new Integrated Materials SolutionsTM for creating ideal GAA gate oxides and metal gates.”

EUV is more energetic laser, so it is difficult to achieve what is called as etch resiliency for a near-perfect EUV pattern transfer uniformity across the entire wafer. Applied has introduced a new the Stensar Advanced Patterning Film for EUV which is deposited using Applied’s Precision CVD (chemical vapor deposition) system, which is an improvement over its own previous spin-on technology.

Applied said its new Sym3 Y etch systems which enables customers to etch and deposit materials in the same chambers to help improve EUV patterns before they are etched into the wafer. "The Sym3 chambers gently remove EUV resist materials and then redeposit material in a special way that averages out the pattern variability caused by “stochastic errors.” The improved EUV patterns increase yields and improve chip power and performance. As a result, Applied’s Sym3 technology is quickly growing beyond memory – where Applied is the number-one supplier of conductor etch systems to the DRAM market – to foundry-logic." stated in the Applied' release.

In the metrology front, Applied's PROVision eBeam metrology technology enables viewing deeply within multilayer chips and do precision measurement of EUV-patterned features on entire wafer. This solves the problem of “edge placement errors”.

Gate All Around transistors are more like FinFETS strucure, where the fins are laid down horizontally instead of vertically. Gate all-around ensures even channels widths. So that GAA ensures better power and performance compared to FinFETs.

However the making of GAA channels involve epitaxy and selective materials removal, where consistency in width and uniformity need to be ensured for optimum power and performance. Applied said it has pioneered selective materials removal when it launched the Selectra system in 2016 and is the market leader with over 1,000 chambers in use by customers.

"A major challenge of manufacturing GAA transistors is that the space between the channels is only around 10nm, and customers must deposit the multilayer gate oxide and metal gate stacks around all four sides of the channels in the minute space available." says Applied.

The new IMS (Integrated Materials Solution) system for the gate oxide stack reduces equivalent oxide thickness by 1.5 angstroms, enabling designers to increase performance with no increase in gate leakage or keep performance constant and reduce gate leakage by more than 10X. It integrates atomic layer deposition (ALD), thermal steps, plasma treatment steps and metrology in a single, high-vacuum system.

Applied said it is demonstrating an IMS system for engineering GAA metal gate stacks, enabling customers to vary gate thicknesses in order to tune transistor threshold voltages to meet the performance-per-watt goals of specific computing applications ranging from battery-powered mobile devices to high-performance servers. It performs the high-precision metal ALD steps in high vacuum to prevent atmospheric contamination.

Author: Srinivasa Reddy N
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