Applied' etch, deposit, test tech enables nm-shrinking of chips using EUV

As the top-notch semiconductor fabrication industry picks up angstroms as units instead of nanometres, the difficulty in shrinking the size of transistor is reaching new heights. In such a situation only few companies able to successfully do research and development to make chips at nodes less than 2 nm. Applied Materials supports two dimensional scaling with Extreme ultraviolet litho in fabricating 3D Gate-All-Around transistors. Although extreme ultraviolet (EUV) lithography enables to print smallest patterns on wafer, there are challenges on material deposition, etching and metrology. Industry is trying to achieve scaling in all dimensions. With the classic Moore's Law 2-D scaling throwing a lot more challengers, chip industry has already pioneered a lot of technologies including backside power distribution networks and Gate-All-Around (GAA) transistors. Along with the improvement in power performance and area (PPA), cost and time-to-market factors getting added to this. So the PPA is becoming PPACt (power, performance, area, cost and time-to-market), as stated in a press release from Applied Materials. “Applied’s strategy is to be the PPACt enablement company for our customers, and today we are presenting seven innovations designed to enable customers to continue 2D scaling with EUV,” said Dr. Prabu Raja, Senior Vice President and General Manager of the Semico...