CoE by Applied and BE Semi to speed up development 3D fabrication of chiplets

Date: 27/10/2020
To address the growing demand for semiconductor equipments to manufacture three-dimensional chips using heterogeneous materials, semiconductor equipment makers Applied Materials and BE Semiconductor have signed agreement to develop the industry’s first complete and proven equipment solution for die-based hybrid bonding. With the cost and technology limitations slowing any further commercially viable growth in 2-D integration of silicon devices, chip industry is looking at more viable 3-D fabrication. 3D IC is like a multi-storey building of 2-D chips electrically interconnected through copper.

Applied and BE Semiconductor to provide hybrid bonding solutions where it uses direct copper to copper interconnects in such a way that the signal integrity is maintained by having a shorter and less interference free copper interconnects. The 3-D chip packs 2D chips of processor, memory, RF and analog in a single stack. Extraordinary performance for applications such as 5G and AI chips can be integrated in a single 3-D chip. Since each of the functional blocks are fabricated separately and may use different semiconductor material processes, which calls for heterogeneous material fabrication.

Applied and BE Semi are establishing a Center of Excellence focused on next-gen chip-to-chip bonding technology so that they can leverage both the companies front and back-end semiconductor fabrication technologies and expertise to design and develop process and equipments for bonding and wiring 2-D chips into 3-D single extremely complex system in a package. Joint development program brings together Applied’s Semiconductor process expertise in etch, planarization, deposition, wafer cleaning, metrology, inspection and particle defect control with BE Semi’s leading die placement, interconnect and assembly solutions.

The 2-D chips in die form are called chiplets. Each of these chiplets can be from different fabs, of different nm nodes, of different materials, and of different functions. Using separate chiplets for each functions ensures reduction in the complexity compared to design of homogeneous single material SoC.

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The release from Applied says "Hybrid bonding is a major improvement over conventional chip packaging because it permits increased chip density and shortens the lengths of the interconnect wiring between chiplets, thereby improving overall performance, power, efficiency and cost."

“Challenges in conventional Moore’s Law scaling are straining the economics and pace of the semiconductor industry’s roadmap,” said Nirmalya Maity, Corporate Vice President of Advanced Packaging at Applied Materials. “Our collaboration with Besi and the formation of a new Hybrid Bonding Center of Excellence are key components of Applied’s strategy to equip customers with a ‘New Playbook’ for driving improvements in PPACt. Applied looks forward to working with Besi to co-optimize our equipment offerings and accelerate advanced heterogeneous integration technology for our customers.”

“We are excited about forming this unique joint development program with Applied Materials which brings together the semiconductor industry’s leading materials engineering and advanced packaging technologies for customers,” said Ruurd Boomsma, CTO of Besi. “Our collaboration can greatly accelerate the adoption and proliferation of hybrid bonding for leading-edge 5G, AI, high-performance computing, data storage and automotive applications.”

The CoE is located at Applied’s Advanced Packaging Development Center in Singapore.

Author: Srinivasa Reddy N
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