Semiconductor Packaging

CoE by Applied and BE Semi to speed up development 3D fabrication of chiplets

To address the growing demand for semiconductor equipments to manufacture three-dimensional chips using heterogeneous materials, semiconductor equipment makers Applied Materials and BE Semiconductor have signed agreement to develop the industry’s first complete and proven equipment solution for die-based hybrid bonding. With the cost and technology limitations slowing any further commercially viable growth in 2-D integration of silicon devices, chip industry is looking at more viable 3-D fabrication. 3D IC is like a multi-storey building of 2-D chips electrically interconnected through copper. Applied and BE Semiconductor to provide hybrid bonding solutions where it uses direct copper to copper interconnects in such a way that the signal integrity is maintained by having a shorter and less interference free copper interconnects. The 3-D chip packs 2D chips of processor, memory, RF and analog in a single stack. Extraordinary performance for applications such as 5G and AI chips can be integrated in a single 3-D chip. Since each of the functional blocks are fabricated separately and may use different semiconductor material processes, which calls for heterogeneous material fabrication. Applied and BE Semi are establishing a Center of Excellence focused on next-gen chip-to-chip bonding technology so that they can leverage both the companies front and back-e...
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