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  Date: 25/09/2016

State-of-art VLSI verification discussed at DV-CON India 2016

The first time silicon tape out success, is no more a wish, its increasingly becoming a necessity for SOC chip designers targeting consumer electronics market and any such large volume time sensitive market. To achieve that, both design and verification gets complex and expensive. With the window of opportunity getting narrower and narrower, the time to design is a challenge. Design team are ready to invest more in the design stage and verification so that they can save cost from the delays, and re-spins.

IOT is one of the application area where SOC designers are challenged with fast turnaround. So what are the VLSI verification trends now leading SOC design companies such as Qualcomm, Broadcom are following? DVCON India 2016 event provided some of the answers related to verification trends.

Speakers at DVCON 2016 explained how different VLSI programming languages such as system Verilog, system C, C++, UVM competing with each other, where no one is clear winner. Every latest language still has its own benefits and drawbacks.

If you look at different methods of VLSI verification, VLSI design engineers are exploring formal, simulation, emulation, and FPGA prototyping based on the requirements and to achieve the goal of first-time successful silicon tape out faster. All the four methods are relevent depending on the type of chip design.

Emulation is expensive but is helping a lot in saving time in specific cases of chip design. Today's emulation systems are powered by data centers to handle billion gate plus chips. These modern emulation systems can also be used in parallel. Some of the leading emulators in the market includes Cadence' Palladium Z1 , Mentor Graphics' Veloce, Synopsys' Zebu, Aldec, HES-DVM, Bluespec' Semu, and also from Dini Group, S2C and HyperSilicon. Cadence Palladium caters to evaluating IP to full SoC with up to 9.2 billion gates, looks to be best of the breed for time being. Its a fast changing world keep tracking and talk to your favourite EDA vendor.

The experts also suggested seamless flow of VLSI code at every stage of chip design across different EDA tools. SoC designers does not stick to any particular vendor, they use tools from multiple vendors for different stages and purposes based on the performance.

So leverage virtual world to design your physical chip. Otherwise you will be a stone-age VLSI designer compared to others. If you're VLSI verification design engineer looking for career upgrade, add the skills of how to use top three emulation tools.

More detailed article on the same subject will be published in the coming weeks.
Author: Srinivasa Reddy N
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