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  Date: 06/06/2016

Micrium' µC/OS-III RTOS ported into EnSilica' eSi-RISC processor cores

If you are a µC/OS-III real time Operating System user and intended or interested in using EnSilica's eSi-RISC processor cores, the software and silicon are made to work well. Micrium’s µC/OS-III is now can be ported to eSi-RISC which also includes Micrium’s range of communication software such as USB host/USB device and TCP/IP networking protocol stack.

Micrium's µC/OS is one of the most widely used RTOS in the world particularly in MCU application which require small footprint/less memory space consuming RTOS. Micrium's µC/OS typically takes 6-24 KBytes of code space and 1 KByte of data space. Micrium µC/OS-III RTOS is made portable to lot of other SoC chips recently which includes Xilinx' Programmable SoC Zynq, Cortus' 32-bit processor cores.

Jean Labrosse, President and CEO of Micrium said combination of µC/OS-III and eSi-RISC is already bearing fruit with joint projects already underway.

To make µC/OS more safer Micrium has recently announced the integration of Icon Labs’ Floodgate Security Framework with its µC/OS-III RTOS.

Scalable Micrium’s µC/OS-III is a pre-emptive and deterministic multi-tasking RTOS with optional round-robin scheduling and supports unlimited application tasks and kernel objects. µC/OS-III is used in safety-critical and risk-averse applications being pre-certified to avionics (DO-178B Level E up to Level A), industrial control (IEC 61508 Safety Integrity Level 1 up to Level 3) and medical (ISO 62304 Class A up to Class C [FDA 510(k)]) standards requirements.

EnSilica’s eSi-RISC is a configurable, scalable, low-power soft processor cores for embedded systems that support both 16-bit and 32-bit configurations. eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSi-3250 32-bit processor, eSi-3250sfp incorporating a single precision floating point processor, eSi-3260 32-bit processor with SIMD DSP extensions and eSi-32X0MP 32-bit scalable, asymmetric multicore processor. The processor cores also benefit from a configurable memory architecture and configurable cache options.

EnSilica has also recently launched the eSi-ECDSA cryptographic IP for automotive v2v and v2x systems. EnSilica is present at the 53 DAC ongoing event from 5th to 9th June in Austin, Texas.
Author: Srinivasa Reddy N
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