Cadence, Mentor and Breker working together in defining SOC verification std

VLSI EDA software companies Cadence Design Systems, Mentor Graphics and Breker Verification Systems are working with Accellera Portable Stimulus Working Group in defining a system-on-chip (SoC) verification standard that offers both vertical (intellectual property to SoC) and horizontal (simulation to post-silicon) reuse of stimulus and test. The collaborative contribution includes: A concise specification language for use-cases that allows high level abstraction of stimulus and tests, including coverage and results checking Semantics to allow generation of tests by automation tools in a variety of languages and tool environments with consistent behavior across multiple implementations from simulation through emulation to FPGA and post-silicon A model-based approach supporting graph-based descriptions of stimulus and test scenarios A library of predefined utility functions plus support for user-defined functions helpful when generating system-level portable stimulus and tests For more information on the Portable Stimulus Working Group, visit http://www.accellera.org/activities/working-groups/portable-stimulus “When we initiated the portable stimulus project within Accellera and offered technology we have in use today, we sought to collaborate with other leading vendors and their technologies to create a standard that would enjoy broad and rapid adoption,” sta...