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  Date: 23/08/2015

IC chip design trends discussed at CDNLive India 2015

EDA software vendor Cadence held its CDNLive India 2015 event on 18th and 19th of Aug in Bangalore. The event as usual talked about latest industry trends on general electronics industry and also specific to VLSI/semiconductor industry. Lip-Bu Tan, president and CEO of Cadence talked more about smart home and automotive electronics.

He highlighted the features in Smart home such as smart thermostat, airconditioner which follows weather, detects occupancy, learning patterns, adjust energy use. And in automotives, trends such as explosion in vision processing, fusion of sensors, cabin acoustics, electronic mirrors, always aware systems sensing sound movement, position sensing are the features driving the design requirement of both electronics as well as chips inside them.

Today, between 3/4th of all car innovations are based directly or indirectly on semiconductors. Car makers around the world thinking over the idea of internal chip design team.

Smart home is one system of subsystems and smart-automotive is another such system of subsystems. In today's interconnected world, your personal digital device, cloud computers/data centers, smart home and automotive has to work together like a system of systems, where functional safety gains exponential importance. Lip Bu Tan presented a video on how system of systems are evolving. Connected smart homes, smartcars with many such other smart things make up smart city, which is basically a another big system of systems. Medical electronics was also mentioned in the Lip Bu's talk.

All these trends finally drive the semiconductor market, Lip Bu Tan said that there is lot of activity in the 14 nm and 16 nm VLSI design, and some of the leading-edge companies are already into 10 nm and 7 nm VLSI.

When the revenues not growing up for semiconductor companies, they press the innovation button harder and the research grows faster to deliver products to enhance the human life. That looks to be happening because there is no significant revenue growth.

As usual, the challenges and complexities increase at the deeper nodes. A lot more verification, a lot more software, a lot more IP blocks, hardware and software qualification.

Lip Bu Tan also touched upon how OEM system companies such as Huawei and Cisco have decided to integrate vertically. There are many system companies designing their own chips for internal use, this is a big trend.

In last 18 months, Cadence has developed faster and time-saving EDA tools, with much more automation and error preventing functions/features. Cadence claims some of its tools takes days instead of weeks for some of the key VLSI design processes.

How can be an electronics engineering keynote 2015 ends without talking about IOT. Mahesh Mehendale, MCU Chief Technologist and director of Kilby Labs India at Texas Instruments highlighted the importance of power saving in IoT product design where your DC/DC converter to front end analog's power performance matters along with choosing the best digital IC.

CDN Live India

Pic: Lip Bu Tan (Far left) with other Cadence executives at the CDN Live

CDN Live India

Pic: Lip Bu Tan giving a gift to Mahesh Mehendale, TI appreciating his talk

The best paper award winners at the event were:

RTL-to-Signoff: Digital Implementation by ARM for the paper titled: “3GHz and beyond” – Jumping To The New Performance Spectrum With ARM Cortex-A72

RTL-to-Signoff: Front-End Design byTexas Instruments for the paper titled "Seamless Deployment Of MSS With Smart-Scan Solution To Enable Higher Multi-Site Test for Large Scale SoCs"

RTL-to-Signoff: Signoff by Open-Silicon for the paper titled "Metal Programmable Clock Delay Line"

Mixed-Signal Design by Texas Instruments for the paper titled "Surviving Eternal Conflict Of Accuracy And Cost – Efficient Analog Mixed Signal Co-simulation With Spectre-XPS-MS"

Custom IC/Analog Design by STMicroelectronics for the paper titled "Addressing 14 FDSOI Custom Routing Complexity Through Existing ST + Cadence Solutions"

System / Verification by Samsung Research Institute - Bangalore for the paper titled "Incremental And Configurable Verification Strategies For Modern SoCs"

System / Verification: Performance & Debug bySilabTech for the paper titled "Modeling And Verification Using System Verilog In Virtuoso And Incisive Enterprise Simulator (NCSIM)"

System / Verification: Hardware Assisted HW/SW Development by Freescale Semiconductor for the paper titled "Methods For Enabling BootROM Firmware Code Coverage on Palladium"

System / Verification: Formal Verification by Qualcomm for the paper titled "SLICE System – SoC Level Inter Connection Extractor"

PCB Design & IC Packaging by Tata Motors Pune for the paper titled "Advantages Of Cadence Simulation Tools In Automotive ECU Environment"
Author: Srinivasa Reddy N
Header ad Author: Srinivasa Reddy N
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