FDSOI interest jump-up with 22nm FDSOI fab from Globalfoundries
For some reason, Fully Depleted Silicon on Insulator (FDSOI) chip fabrication technology was pushed down by the major foundries and have taken FinFET path further to the 28 nm node. Many of the industry experts argue that 22 nm FDSOI chip can give the benefits what 14 nm finFET device can give in majority of applications. Except for the expensive silicon wafer cost and little different CAD implementation of VLSI design, the total cost of 22 nm FDSOI chip is lesser than finFET chip. FDSOI requires far lesser masks than the 14 nm finFET.
Though late, chip industry has realised the potential benefit of fully depleted silicon on insulator technology. Now you have a fab/foundry by Globalfoundries which makes chips at the cost of 28 nm bulk, but the performance benefits near equivalent to 14 nm finFETs. IOT and the low-cost smart phones are the two important markets for this technology.
The 22 nm FDSOI platform called “22FDX” is suggested as optimal solution for mainstream mobile, Internet-of-Things (IoT), RF connectivity and networking markets, where cost is the driving factor.
From this 22FDX process you get a lowest operating voltage of 0.4V, 20% smaller die size, a 10% lesser masks compared to 28 nm and nearly 50 percent fewer immersion lithography layers than foundry FinFET, says Globalfoundries.
22FDX also features a real-time system software control of transistor characteristics where system designer can dynamically balance power, performance, and leakage.
Globalfoundries 22FDX 300mm production line is located in Dresden, Germany.
22FDX platform consists of a family of differentiated products architected to support the needs of various applications: below are the differentiated products and its features shared by Globalfoundries:
22FD-ulp: For the mainstream and low-cost smartphone market, the base ultra-low power offering provides an alternative to FinFET. Through the use of body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.
22FD-uhp: For networking applications with analog integration, this offering is optimized to achieve the same ultra-high performance capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.
22FD-ull: The ultra-low leakage offering for wearables and IoT delivers the same capabilities of 22FD-ulp, while reducing leakage to as low as 1pa/um. This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.
22FD-rfa: The radio frequency analog offering delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.
Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.
Jean-Marc Chery, COO of STMicroelectronics finds FD-SOI as an ideal process for low-power requirements of IoT and other power-sensitive devices worldwide.
Wayne Dai, president and CEO of VeriSilicon, the company which has experience in designing IoT SoCs in FD-SOI technology sees higher potential in 22FDX for designing chips for smart phones, smart homes, and smart cars for the China market.
Soitec which makes the FDSOI silicon wafers is ready with ultra-thin SOI substrate for high-volume manufacturing of 22FDX technology.
So if 22 nm FDSOI is so interesting and ready, what will happen to the 14 and 16 nm fabs and foundries around the world. They will be mostly used for making complex chips for server computers, PCs, and also expensive phones like iPhones. Here TSMC, UMC, SMIC has got something to worry which still has not announced any plans to get into FDSOI production. Intel, more of a high-end processor market dependent company has much less to worry, but still affected by IOT, wearable and low-cost smart phone market which may show more interest in FDSOI ARM powered chips rather than x86.
With 14nm fin FET capability, and access to 10 nm and 7 nm technologies from IBM, and this FDSOI push gives Globalfoundries a strong launchpad in overtaking TSMC.
Those who don't know what is FDSOI below is a brief explanation of FDSOI and also the benefits it offers as answered by Rajamohan Varambally, Director, Central CAD and design solutions, ST Microelectronics India.
Planar fully depleted silicon-on-insulator (“planar FD”, or equivalently “FD-SOI”) transistors are planar CMOS transistors fabricated in a very thin layer of silicon sitting over a layer of buried oxide (BOX). They are therefore ‘ultra-thin body’ (UTB) devices: the electrical conduction channel that forms between source and drain is confined to this ultra-thin silicon layer under the gate oxide.
What makes this process better than other deep-node semiconductor chip fabrication tech?
1. Immunity to Short-Channel Effects:
Ultra-thin body and BOX ensures all electrical paths between source and drain are very close to the gate, and the latter therefore maintains excellent electrostatic control over the channel. As a result, sub-threshold slope, DIBL and other short-channel effects exhibit excellent values.
2. Reduced Variability:
· The absence of doping or pocket implants in the channel helps to control the electrostatic characteristics and tune the threshold voltages. No doping or implants eliminates the major issue of random dopant fluctuation.
3. Low source/drain capacitance, lower leakage and latch-up immunity due to BOX.
If fabless companies decide to use FD-SOI process, what are the issues they should address while moving their design to FD-SOI?
The design method and tools used in 28nm bulk is applicable to FD-SOI as well. Using the foundation IPs and Physical DK provided by ST, any fabless company can make their design in FD-SOI. IP blocks have to be FD-SOI compatible; if not, those blocks need to be migrated. ST has proven that the porting effort is not difficult or challenging.
Can FD-SOI be used for chips other than logic such as analog and RF?
FD-SOI analog performance is far better than Bulk. It is faster, provides better gain and better parasitic-capacitance noise immunity. This translates into easier design and better performance for RF, mixed signal and high speed interfaces like serializers/deserializers.
Q. Finally can FD-SOI help semiconductor industry still extend Moore's Law into deeper nodes such as 7 nm?
1. In the past, the cost per gate decreased each time the industry moved to a new technology node. From 20 nm onwards the cost per gate increases. So by choosing 28nm FD-SOI, the customer delays this effect. In the meantime the industry will see an improvement in cost, performance and power efficiency compared to the previous node (See the below picture).
2. UTBB FD-SOI is scalable down to 10nm Technology Node. Electrostatic control achieved by thinning Tbox (See the below picture).
Author: Srinivasa Reddy N