Date: 10/08/2015

Monolithic 3-D IC fabrication, a vertically integrated CMOS transistors

Semiconductor engineers finding various ways to take the Moore's law further down the 7 nm, though physics supports but there are cost wise constraints. One of the best way to pack more transistors in a given area is to fabricate transistors vertically one above the other. Unlike building construction where the next floor is built without disturbing the bottom floor, in 3D semiconductor chip fabrication when the semiconductor layers/floors are processed/fabricated, temperatures rise to the range of 1000 degree centigrade, the bottom-layer/floor transistors gets destroyed while you build the top layer. To solve this problem researchers find some cool technologies to fabricate the transistor layers within the allowed/budgeted temperature.

The idea of placing separate wafers one over the other and connecting them using through silicon vias, looks to be less reliable and complex, with limitations in number of interconnections, and is not that beneficial in performance. If not exactly called monolithic, the sequential fabrication of 3-D IC looks to be realistic based on the research outcome by leading nanoelectronics researcher CEA Leti. CEA Leti call this technology as CoolCube. CEA Leti uses tungsten material as interconnect, where it has found a way to fabricate the interconnects using lithography techniques.

CEA Leti also reported it could advance CoolCube feasibility in FinFET technology on its 300mm production line, and new CoolCube circuit designs that improve the trade off between area, speed and power.

CEA Leti has progressed from demonstration of single device to taking the technology for fabrication.

This technology allows backside imagers in the chips, and co-integration of NEMS(Nano mems) in a CMOS fabrication process also is possible. You can have a 3-D IC where one side is the image sensor and other side is the logic and memory, that's basically SoC with integrated image sensor.

“CoolCube enables local via density that is 10,000 times higher than ‘standard’ 3D integration, because the technology is designed to connect stacked active layers at a nanometric scale,” said Maud Vinet, Leti’s advanced CMOS laboratory manager. “In the digital area, we expect this 3D technique to allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation. In heterogeneous integration, we expect CoolCube to be an actual enabler of smart-sensor arrays by allowing a close integration of sensors, detection electronics and digital signal
processing.”



Author: Srinivasa Reddy N
Author: Srinivasa Reddy N