Monolithic 3-D IC fabrication, a vertically integrated CMOS transistors

Semiconductor engineers finding various ways to take the Moore's law further down the 7 nm, though physics supports but there are cost wise constraints. One of the best way to pack more transistors in a given area is to fabricate transistors vertically one above the other. Unlike building construction where the next floor is built without disturbing the bottom floor, in 3D semiconductor chip fabrication when the semiconductor layers/floors are processed/fabricated, temperatures rise to the range of 1000 degree centigrade, the bottom-layer/floor transistors gets destroyed while you build the top layer. To solve this problem researchers find some cool technologies to fabricate the transistor layers within the allowed/budgeted temperature. The idea of placing separate wafers one over the other and connecting them using through silicon vias, looks to be less reliable and complex, with limitations in number of interconnections, and is not that beneficial in performance. If not exactly called monolithic, the sequential fabrication of 3-D IC looks to be realistic based on the research outcome by leading nanoelectronics researcher CEA Leti. CEA Leti call this technology as CoolCube. CEA Leti uses tungsten material as interconnect, where it has found a way to fabricate the interconnects using lithography techniques. CEA Leti also reported it could advance CoolCube feasibili...