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  Date: 10/08/2015

Semicon West: Forget microelectronics itís not even nano letís call it atomtronics

The era of atomic level control of electrical properties have already begun, in that sense the so-called Mooreís law will continue but with the new way of doing things. The researchers in semiconductor manufacturing are both engineers and also equally good material scientists who always explored how to find a way around the technology barricades/walls and also design a manufacturing process in such a way that it can be manufactured in volumes at a cost feasible for business success. So it takes a huge amount of scientific as well as engineering talent and also business knowledge of the industry in this field of semiconductor research.

The less expensive and simple processes are explored first compared to the complex ones. Now engineers are thrown out with two paths to take, one is FDSOI and other is finFET. FDSOI suddenly finds some increase in interest, Globalfoundries is investing in building a 22 nm FDSOI fab, Samsung has already have it along with STMicroelectronics' FDSOI fab in France. Monolithic 3D IC is also progressing faster check-out CEA Leti's CoolCube tech.

The material magic: Its no more silicon alone, Germanium has already given a grand entry. The 7 nm test-chips taped out by IBM have used silicon germanium material. Well, you have the whole periodic table to explore to take further down the 7 nm. Compound semiconductors are performing better than silicon at deeper nodes.

Mixing of different semiconductor material is the art of epitaxial growth of semiconductor material of one-type over the other basically managing lattice mismatch. It is called heteroepitaxy. Silicon Germanium preferred for high level of charge mobility, Gallium Arsenide CMOS will be offering even more higher mobility, but a bigger challenge in laying a layer of Gallium Arsenide over silicon.

The printing based lithography is not sufficient, self-assembly concepts are well under consideration at 7 nm and smaller. Semiconductor industry is now using multiple patterning up to 10 nm. Multiple patterning is complex and need more number of masks which increases the total cost of the chip. At 7 nm and down extreme ultraviolet EUV is used but there are issues such as lack of enough light power. EUV brings down both mask per device and steps per mask. Sensitive photo-resist is also a issue in EUV.

Tools from semiconductor equipment vendors:
The new tool from Lam Research enhances the dielectric etching of high-aspect-ratio (HAR) capacitor cells and vertical transistor channels in DRAM and 3D NAND flash, where the tool named Flex G Series uses RF pulsing with high ion energy.

Lam Research has also announced atomic layer deposition (ALD) oxide deposition system for creating dielectric films supporting multiple patterning, particularly the spacer-based multi-patterning such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

Lam has shipped its 200th Kiyo conductor etch module with proprietary Hydra technology

TEL NEXX's new Stratus P300, electrochemical deposition (ECD) tool features denser wafer plating positions supporting longer plating applications, such as copper pillar, interposer and fan-out wafer level packaging. For shorter plating time applications, like copper redistribution layers (RDL), the Stratus P300' s high speed wafer handling system supplies higher throughput. P300 also support Through Silicon Via (TSV) and Through Mold Via (TMV).

Applied Materials has unveiled its new Applied Olympia ALD system featuring a modular architecture for ALD technology targeting 3D memory and logic chips.
Applied Materials's new etch tool, the Applied Centris Sym3 Etch system chamber uses multiple tuning controls for optimizing global process uniformity to the atomic level. This tool also has better control and removal of etch byproducts, which are a problem in achieving patterning uniformity.

Semiconductor equipment market:
If you look at the latest semiconductor equipment market forecast, SEMI has forecasted the total semiconductor equipment market will grow 7 percent in 2015 (reaching $40.2 billion) and expand another 4 percent in 2016 to reach $41.8 billion.

More on the 200mm 450mm and on-chip photonics in next article.
Author: Srinivasa Reddy N
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