VLSI design: Fab your semiconductor chip virtually

In semiconductor chip fabrication, up to 90 nm node, the challenge was more of printing smallest patterns on photoresist material to carry out successful lithography of a planar silicon wafer/disk. In this era of 14 nm and lesser node chip fabrication, it was more of a material and structural changes including three-dimensional transistors. As the structural and material complexity enters down the 14nm node, semiconductor and nanotechnology researchers while developing new ideas, they don't really need to fabricate a real device, instead they can use virtual fabrication tool/software, basically computer simulated structural/behavioral simulation of their new ideas/development. VLSI design is already driven by heavy use of software tools from concept to production, but they are dependent on chip-fabs to make the real sample chip, now that can be done virtually in your computer. From three-dimensional finFETs, silicon photonics, mems to three-dimensional memory stacking, Virtual fabrication environment saves semiconductor designers time and money in fabricating the real device. Virtual fabrication is extremely relevant for more than Moore technology such as system on module (SOM), system in package (SIP), 3D IC kind of single device non-monolithic assembly of subsystems. Same technology can also be used for designing highly compact printed circuit board such as smart phon...