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  Date: 22/03/2015

ARM and Cadence to support each other's Ips

Cadence Design Systems and ARM signed broad IP Interoperability Agreement where each one's customers get access to relevant IP portfolios from both Cadence IP Group and ARM. This agreement also allows both the companies to fabricate test chips containing Cadence IP and ARM IP. All this aimed at optimising performance and interoperability of IPs from ARM and cadence for fast-growing applications in the areas of mobile, consumer, networking, storage, automotive and the Internet of Things (IoT). Its like if you are using IP and design services from Cadence you get all the support related to ARM, and same in case of opposite.

The IP Interoperability agreement covers existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink system IP, ARM Artisan physical IP, and ARM POP IP; Cadence Design IP including cores for PCI Express, MIPI, USB, HDMI, DisplayPort, Ethernet, analog, DDR/LPDDR PHY and multiple other memory and storage protocols.

"This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable our customers' designs to reach peak performance and power efficiency," said Pete Hutton, executive vice president and president of product groups, ARM. "Extending our collaboration with Cadence to IP interoperability means we are mutually embracing the increasing importance of optimizing the IP systems within SoC designs. By working together closely, we can continue to deliver the key technologies that allow our customers to push the boundaries of innovation."

"Through expanded collaboration, Cadence and ARM are able to develop and deliver solutions that enable our customers to rapidly design optimized high-performance ARM-based SoCs and speed time to market for complete systems," said Martin Lund, senior vice president, IP Group at Cadence. "This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design."
Author: Srinivasa Reddy N
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